A model and implementation of a universal time delay simulator for large digital nets. - Stephen A. Szygenda; David M. Rouse; Edward W. Thompson (AFIPS Spring Joint Computing Conference, 1970)

Fault insertion techniques and models for digital logic simulation. - Stephen A. Szygenda; Edward W. Thompson (AFIPS Fall Joint Computing Conference (2), 1972)

Timing analysis for digital fault simulation using assignable delays. - Edward W. Thompson; Stephen A. Szygenda; N. Billawala; R. Pierce (DAC, 1974)

A module interface specification language. - Edward W. Thompson; Robert F. Bridge (DAC, 1975)

The software engineering technique of data hiding as applied to multi-level model implementation of logical devices in digital simulation. - Edward W. Thompson; N. Billawala (DAC, 1975)

Three levels of accuracy for the simulation of different fault types in digital systems. - Edward W. Thompson; Stephen A. Szygenda (DAC, 1975)

Digital Logic Simulation in a Time-Based, Table-Driven Environment. - Edward W. Thompson; Stephen A. Szygenda (Computer, 1975)

Bridges: a tool for increasing the reliability of references to Fortran variables. - Robert F. Bridge; Edward W. Thompson (ACM SIGPLAN Notices, 1976)

Modeling and Digital Simulation for Design Verification and Diagnosis. - Stephen A. Szygenda; Edward W. Thompson (IEEE Trans. Computers, 1976)

The incorporation of functional level element routines into an existing digital simulation system. - Edward W. Thompson; Patrick G. Karger; W. R. Read Jr.; Don Ross; John Smith; Richard von Blucher (DAC, 1980)

An accurate functional level concurrent fault simulator. - Manuel A. d'Abreu; Edward W. Thompson (DAC, 1980)