Arria™ 10 device architecture. - Jeffrey Tyhach; Mike Hutton; Sean Atsatt; Arifur Rahman; Brad Vest; David M. Lewis; Martin Langhammer; Sergey Y. Shumarayev; Tim Hoang; Allen Chan; Dong-Myung Choi; Dan Oh; et al. (CICC, 2015)

8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO. - Kaveh Hosseini; Edwin Kok; Sergey Y. Shumarayev; Chia-Pin Chiu; Arnab Sarkar 004; Asako Toda; Yanjing Ke; Allen Chan; Daniel Jeong; Mason Zhang; Sangeeta Raman; Thungoc Tran; et al. (OFC, 2021)

5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O. - Kaveh Hosseini; Edwin Kok; Sergey Y. Shumarayev; Daniel Jeong; Allen Chan; Austin Katzin; Songtao Liu; Radek Roucka; Manan Raval; Minh Mac; Chia-Pin Chiu; Thungoc Tran; et al. (VLSI Technology and Circuits, 2022)