A low jitter triple-band digital LC PLL in 130nm CMOS. - Nicola Da Dalt; Edwin Thaller; Peter Gregorius; Lajos Gazsi (ESSCIRC, 2004)

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS. - Nicola Da Dalt; Edwin Thaller; Peter Gregorius; Lajos Gazsi (IEEE J. Solid State Circuits, 2005)

Digital compensation of DC-DC converter voltage ripple for Switched-Capacitor Power Amplifiers. - Stefan Trampitsch; Daniel Gruber; Michael Lunglmayr; Edwin Thaller; Mario Huemer (NEWCAS, 2016)

13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE. - Antonio Passamani; Davide Ponton; Edwin Thaller; Gerhard Knoblinger; Andrea Neviani; Andrea Bevilacqua (ISSCC, 2017)

A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS. - Edwin Thaller; Run Levinger; Evgeny Shumaker; Aryeh Farber; Sergey Bershansky; Nir Geron; Ashoke Ravi; Rotem Banin; Jasmin Kadry; Gil Horovitz; Christian Krassnitzer; Christoph Duller; et al. (ISSCC, 2021)