Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems. - Shigeo Kaneda; Eiji Fujiwara (IEEE Trans. Computers, 1982)

A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing. - Eiji Fujiwara; Nobuo Mutoh; Kohji Matsuoka (IEEE Trans. Computers, 1984)

A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing. - Eiji Fujiwara; Kohji Matsuoka (IEEE Trans. Computers, 1987)

Masking asymmetric line faults using semi-distance codes. - Kazumitsu Matsuzawa; Eiji Fujiwara (FTCS, 1988)

Fault - tolerant k - out - of - n logic unit networks. - Eiji Fujiwara; Kohji Matsuoka (Syst. Comput. Jpn., 1988)

Error-control coding for computer systems. - Thammavarapu R. N. Rao; Eiji Fujiwara (Prentice Hall, 1989)

Error-Control Coding in Computers. - Eiji Fujiwara; Dhiraj K. Pradhan (Computer, 1990)

Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems. - Eiji Fujiwara; Mitsuru Hamada (FTCS, 1992)

A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. - Eiji Fujiwara; Masaharu Tanaka (DFT, 1993)

A Probabilistic Measurement for Totally Self-Checking Circuits. - Jien-Chung Lo; Eiji Fujiwara (DFT, 1993)

A Class of Error Locating Codes for Byte-Organized Memory Systems. - Eiji Fujiwara; Masato Kitakami (FTCS, 1993)

A class of error-correcting codes for byte-organized memory systems. - Eiji Fujiwara; Masato Kitakami (IEEE Trans. Inf. Theory, 1994)

A Class of Optimal Fixed-Byte Error Protection Codes for Computer Systems. - Eiji Fujiwara; Masato Kitakami (FTCS, 1995)

Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation. - Eiji Fujiwara; Masaharu Tanaka (IEICE Trans. Inf. Syst., 1995)

Fault-tolerant associate memories. - Eiji Fujiwara; Tsuyoshi Tanaka (Syst. Comput. Jpn., 1995)

Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study. - Jien-Chung Lo; Masato Kitakami; Eiji Fujiwara (DFT, 1996)

Probability to Achieve TSC Goal. - Jien-Chung Lo; Eiji Fujiwara (IEEE Trans. Computers, 1996)

A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-. - Mitsuru Hamada; Eiji Fujiwara (IEEE Trans. Computers, 1997)

Optimal Two-Level Unequal Error Control Codes for Computer Systems. - Eiji Fujiwara; Tepparit Ritthongpitak; Masato Kitakami (IEEE Trans. Computers, 1998)

Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability. - Kiattichai Saowapa; Haruhiko Kaneko; Eiji Fujiwara (DFT, 1999)

Evaluations of Burst Error Recovery for VF Arithmetic Coding. - Masato Kitakami; Hongyuan Chen; Eiji Fujiwara (DFT, 2000)

Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems. - Ganesan Umanesan; Eiji Fujiwara (DFT, 2000)

Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. - Kazuteru Namba; Eiji Fujiwara (DFT, 2001)

A class of systematic t/B-error correcting codes for semiconductor memory systems. - Ganesan Umanesan; Eiji Fujiwara (ITW, 2001)

A class of systematic m-ary single-symbol error correcting codes. - Kazuteru Namba; Eiji Fujiwara (Syst. Comput. Jpn., 2001)

A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems. - Ganesan Umanesan; Eiji Fujiwara (PRDC, 2002)

Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities. - Kazuteru Namba; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Random Double Bit Error Correcting-Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems. - Ganesan Umanesan; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems. - Ganesan Umanesan; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems. - Ganesan Umanesan; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. - Haruhiko Kaneko; Eiji Fujiwara (DFT, 2003)

A Class of Codes for Correcting Single Spotty Byte Errors. - Ganesan Umanesan; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes. - Ganesan Umanesan; Eiji Fujiwara (IEEE Trans. Computers, 2003)

Nonsystematic M-Ary Asymmetric Error Correcting Codes Designed by Multilevel Coding Method. - Haruhiko Kaneko; Mariko Numakami; Eiji Fujiwara (PRDC, 2004)

A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices. - Haruhiko Kaneko; Eiji Fujiwara (IEEE Trans. Computers, 2004)

Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. - Jien-Chung Lo; Yu-Lun Wan; Eiji Fujiwara (DFT, 2005)

A class of error control codes for M-spotty byte errors occurred in a limited number of bytes. - Kazuyoshi Suzuki; Mamoru Shimizu; Toshihiko Kashiyama; Eiji Fujiwara (ISIT, 2005)

Parallel Decoding Cyclic Burst Error Correcting Codes. - Ganesan Umanesan; Eiji Fujiwara (IEEE Trans. Computers, 2005)

Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems. - Hiroyuki Ohde; Haruhiko Kaneko; Eiji Fujiwara (DFT, 2006)

Complex M-Spotty Byte Error Control Codes. - Kazuyoshi Suzuki; Toshihiko Kashiyama; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Joint Source-Cryptographic-Channel Coding Based on Linear Block Codes. - Haruhiko Kaneko; Eiji Fujiwara (AAECC, 2007)

Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. - Haruhiko Kaneko; Eiji Fujiwara (DFT, 2007)

Mac Williams Identity for m-Spotty Weight Enumerator. - Kazuyoshi Suzuki; Haruhiko Kaneko; Eiji Fujiwara (ISIT, 2007)

A General Class of M-Spotty Byte Error Control Codes. - Kazuyoshi Suzuki; Toshihiko Kashiyama; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings. - Kazuteru Namba; Eiji Fujiwara (Syst. Comput. Jpn., 2007)

Three-Level Error Control Coding for Dependable Solid-State Drives. - Haruhiko Kaneko; Takuya Matsuzaka; Eiji Fujiwara (PRDC, 2008)

A Class of Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. - Haruhiko Kaneko; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

M-Ary Substitution/Deletion/Insertion/Adjacent-Symbol-Transposition Error Correcting Codes for Data Entry Systems. - Haruhiko Kaneko; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Joint source-cryptographic-channel coding for dependable systems. - Haruhiko Kaneko; Eiji Fujiwara (Int. J. Comput. Appl. Technol., 2009)

MacWilliams Identity for M-Spotty Weight Enumerator. - Kazuyoshi Suzuki; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)