A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique. - Naoto Tomita; Nobuaki Ohtsuka; Jun-ichi Miyamoto; Ken-ichi Imamiya; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Norihisa Arai; Yukio Kaneko; Eiji Sakagami; Kuniyoshi Yoshikawa; Sumio Tanaka (IEEE J. Solid State Circuits, 1991)