Error suppressing encode logic of FCDL in a 6-b flash A/D converter. - Koichi Ono; Tatsuji Matsuura; Eiki Imaizumi; Hisashi Okazawa; Ryuushi Shimokawa (IEEE J. Solid State Circuits, 1997)

A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. - Tatsuji Matsuura; Takashi Nara; Tatsuya Komatsu; Eiki Imaizumi; Toshihiro Matsutsuru; Ryutaro Horita; Haruto Katsu; Shintaro Suzumura; Kazuo Sato (IEEE J. Solid State Circuits, 1998)

A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop. - Yasutoshi Aibara; Eiki Imaizumi; Hiroaki Takagishi; Tatsuji Matsuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver. - Tatsuo Nakagawa; Tatsuji Matsuura; Eiki Imaizumi; Junya Kudoh; Goichi Ono; Masayuki Miyazaki; Akira Maeki; Yuji Ogata; Shinsuke Kobayashi; Noboru Koshizuka; Ken Sakamura (ESSCIRC, 2007)

1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver. - Tatsuo Nakagawa; Tatsuji Matsuura; Eiki Imaizumi; Junya Kudoh; Goichi Ono; Masayuki Miyazaki (IEICE Trans. Electron., 2009)