Design automation in norway. - P. A. Arneberg; Einar J. Aas (DAC, 1975)

An integrated system for interactive editing of schematics, logic simulation and PCB layout design. - Hedayat Markus Bayegan; Einar J. Aas (DAC, 1978)

Test generation through logic programming. - Dag Svanæs; Einar J. Aas (Integr., 1984)

State transition graph analysis as a key to BIST fault coverage. - Ove Brynestad; Einar J. Aas; Anne E. Vallestad (ITC, 1990)

Experiments with autonomous test of PLAs. - Einar J. Aas; Gunnar Nystu (EURO-DAC, 1991)

Combined probabilistic testability calculation and compact test generation for PLAs. - Bjørg Reppen; Einar J. Aas (J. Electron. Test., 1991)

Verification and Diagnosis of Digital Systems by Termary Reasoning. - Ayman M. Wahba; Einar J. Aas (CHARME, 1993)

Quantifying Design Quality Through Design Experiments. - Einar J. Aas; Tore Steen; Karl Klingsheim (IEEE Des. Test Comput., 1994)

Comparison of two architectures for implementation of the discrete cosine transform. - Ingil Sundsbo; G. Lokken Hansen; Einar J. Aas (ICASSP, 1996)

4300 Megasamples/s Wave Digital Filter Implementation In Bit-parallel Tspc Circuit Technique. - Johnny Pihl; Einar J. Aas (ISSPA, 1996)

A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs. - Øyvind Strøm; Audun Klauseie; Einar J. Aas (EUROMICRO, 1999)

Project based learning objectives and experiences in electronic education: a memory controller design experiment. - Einar J. Aas; Jukka Typpo (ICECS, 1999)

Storage requirement estimation for data intensive applications with partially fixed execution ordering. - Per Gunnar Kjeldsberg; Francky Catthoor; Einar J. Aas (CODES, 2000)

Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering. - Per Gunnar Kjeldsberg; Francky Catthoor; Einar J. Aas (ICCAD, 2000)

On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning. - Sverre Wichlund; Einar J. Aas (ICECS, 2000)

Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences. - Einar J. Aas (ISQED, 2000)

Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications. - Per Gunnar Kjeldsberg; Francky Catthoor; Einar J. Aas (DAC, 2001)

An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code. - Øyvind Strøm; Einar J. Aas (DSD, 2001)

Formal verification of digital circuits by 3-valued simulation. - Ayman M. Wahba; Einar J. Aas (ICECS, 2001)

On the Utilization of Java Technology in Embedded Systems. - Øyvind Strøm; Kjetil Svarstad; Einar J. Aas (Des. Autom. Embed. Syst., 2003)

Data dependency size estimation for use in memory optimization. - Per Gunnar Kjeldsberg; Francky Catthoor; Einar J. Aas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Storage requirement estimation for optimized design of data intensive applications. - Per Gunnar Kjeldsberg; Francky Catthoor; Einar J. Aas (ACM Trans. Design Autom. Electr. Syst., 2004)

Remote Path Delay Fault Simulation. - Øystein Gjermundnes; Einar J. Aas (DSD, 2005)

Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor. - Sverre Wichlund; Einar J. Aas (ATS, 2006)

Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor. - Sverre Wichlund; Frank Berntsen; Einar J. Aas (DFT, 2006)

Probabilistic gate-level power estimation using a novel waveform set method. - Saeeid Tahmasbi Oskuii; Per Gunnar Kjeldsberg; Einar J. Aas (ACM Great Lakes Symposium on VLSI, 2007)

Scan Test Response Compaction Combined with Diagnosis Capabilities. - Sverre Wichlund; Frank Berntsen; Einar J. Aas (J. Electron. Test., 2008)

Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications. - Per Gunnar Kjeldsberg; Francky Catthoor; Sven Verdoolaege; Martin Palkovic; Arnout Vandecappelle; Qubo Hu; Einar J. Aas (J. Signal Process. Syst., 2008)

Design of novel CAM core cell structures for an efficient implementation of low power BCAM system. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (ACM Great Lakes Symposium on VLSI, 2009)

Path-Delay Fault Testing in Embedded Content Addressable Memories. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (DSD, 2010)

Experiments with ABIST test methodology applied to path delay fault testing. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (EWDTS, 2010)

An Enhanced Path Delay Fault Simulator for Combinational Circuits. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (DSD, 2011)

A programmable BIST with macro and micro codes for embedded SRAMs. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas; Mohammad Areef (EWDTS, 2011)

Design of embedded TCAM based longest prefix match search engine. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (Microprocess. Microsystems, 2011)