Variable VCC design techniques for battery-operated DRAMs. - Seung-Moon Yoo; Ejaz Haq; Seung-Hoon Lee; Yun-Ho Choi; Soo-In Cho; Nam-Soo Kang; Daeje Chin (IEEE J. Solid State Circuits, 1993)

16-Mb synchronous DRAM with 125-Mbyte/s data rate. - Yunho Choi; Myungho Kim; Hyunsoon Jang; Taejin Kim; Seung-hoon Lee; Ho-cheol Lee; Churoo Park; Siyeol Lee; Cheol-soo Kim; Soo-In Cho; Ejaz Haq; J. Karp; et al. (IEEE J. Solid State Circuits, 1994)

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. - Jei-Hwan Yoo; Chang-Hyun Kim; Kyu-Chan Lee; Kye-Hyun Kyung; Seung-Moon Yoo; Jung-Hwa Lee; Moon-Hae Son; Jin-Man Han; Bok-Moon Kang; Ejaz Haq; Sang-Bo Lee; Jai-Hoon Sim; et al. (IEEE J. Solid State Circuits, 1996)

JAZiO Signal-Switching Technology: A Low-Cost Digital I/O for High-Speed Applications. - Ejaz Haq; Jim Slager; John Pecoraro; John D. Johnson; Mark Santoro; Lee Tavrow; Scott D. Wakefield; David Weisner (IEEE Micro, 2001)