Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. - Kris Gaj; Ekawat Homsirikamol; Marcin Rogawski (CHES, 2010)

ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs. - Kris Gaj; Jens-Peter Kaps; Venkata Amirineni; Marcin Rogawski; Ekawat Homsirikamol; Benjamin Y. Brewster (FPL, 2010)

Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. - Ekawat Homsirikamol; Marcin Rogawski; Kris Gaj (IACR Cryptol. ePrint Arch., 2010)

Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. - Ekawat Homsirikamol; Marcin Rogawski; Kris Gaj (CHES, 2011)

Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modules. - Benjamin Y. Brewster; Ekawat Homsirikamol; Rajesh Velegalati; Kris Gaj (FPT, 2012)

Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs. - Kris Gaj; Ekawat Homsirikamol; Marcin Rogawski; Rabia Shahid; Malik Umar Sharif (IACR Cryptol. ePrint Arch., 2012)

Security margin evaluation of SHA-3 contest finalists through SAT-based attacks. - Ekawat Homsirikamol; Pawel Morawiecki; Marcin Rogawski; Marian Srebrny (IACR Cryptol. ePrint Arch., 2012)

A Novel Permutation-based Hash Mode of Operation FP and the Hash Function SAMOSA. - Souradyuti Paul; Ekawat Homsirikamol; Kris Gaj (IACR Cryptol. ePrint Arch., 2012)

A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl. - Marcin Rogawski; Kris Gaj; Ekawat Homsirikamol (Microprocess. Microsystems, 2013)

A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs. - Marcin Rogawski; Ekawat Homsirikamol; Kris Gaj (FPL, 2014)

Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study. - Ekawat Homsirikamol; Kris Gaj (ReConFig, 2014)

ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption. - Pawel Morawiecki; Kris Gaj; Ekawat Homsirikamol; Krystian Matusiewicz; Josef Pieprzyk; Marcin Rogawski; Marian Srebrny; Marcin Wójcik (IACR Cryptol. ePrint Arch., 2014)

Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study. - Ekawat Homsirikamol; Kris Gaj (ARC, 2015)

Comparison of multi-purpose cores of Keccak and AES. - Panasayya Yalla; Ekawat Homsirikamol; Jens-Peter Kaps (DATE, 2015)

A universal hardware API for authenticated ciphers. - Ekawat Homsirikamol; William Diehl; Ahmed Ferozpuri; Farnoud Farahmand; Malik Umar Sharif; Kris Gaj (ReConFig, 2015)

GMU Hardware API for Authenticated Ciphers. - Ekawat Homsirikamol; William Diehl; Ahmed Ferozpuri; Farnoud Farahmand; Malik Umar Sharif; Kris Gaj (IACR Cryptol. ePrint Arch., 2015)

AEZ: Anything-But EaZy in Hardware. - Ekawat Homsirikamol; Kris Gaj (INDOCRYPT, 2016)

A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests. - Farnoud Farahmand; Ekawat Homsirikamol; Kris Gaj (ReConFig, 2016)

CAESAR Hardware API. - Ekawat Homsirikamol; William Diehl; Ahmed Ferozpuri; Farnoud Farahmand; Panasayya Yalla; Jens-Peter Kaps; Kris Gaj (IACR Cryptol. ePrint Arch., 2016)

Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study. - Ekawat Homsirikamol; Kris Gaj (FPT, 2017)

A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures. - Ahmad Salman; Ahmed Ferozpuri; Ekawat Homsirikamol; Panasayya Yalla; Jens-Peter Kaps; Kris Gaj (ReConFig, 2017)

A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography. - Jens-Peter Kaps; William Diehl; Michael Tempelmeier; Farnoud Farahmand; Ekawat Homsirikamol; Kris Gaj (IACR Cryptol. ePrint Arch., 2019)