Real time image rotation using B-spline interpolation on FPGA's board. - Cyril Berthaud; El-Bay Bourennane; Michel Paindavoine; Claude Milan (EUSIPCO, 1998)

Implementation of a Real Time Image Rotation using B-Spline Interpolation on FPGA's Board. - Cyril Berthaud; El-Bay Bourennane; Michel Paindavoine; Claude Milan (ICIP (3), 1998)

A Recursive Digital Filter Implementation for Noisy and Blurred Images. - Lionel Torres; El-Bay Bourennane; Michel Robert; Michel Paindavoine (Real Time Imaging, 1998)

A principal component analysis based method for the Simulation of turbulence-degraded infrared image sequence. - Christine Bondeau; El-Bay Bourennane; Michel Paindavoine (Ann. des Télécommunications, 1999)

Approches région et bayésienne pour la restauration ďimages dégradées par la turbulence atmosphérique. - El-Bay Bourennane; Christine Bondeau; Michel Paindavoine (Ann. des Télécommunications, 2001)

Real-time flaw detection on complex part: Study of SVM and hyperrectangle based method. - Sebastien Bouillant; Johel Mitéran; El-Bay Bourennane; Michel Paindavoine (ICASSP, 2002)

Cost comparison of image rotation implantations on static and dynamic Reconfigurable FPGAs. - El-Bay Bourennane; Sophie Bouchoux; Johel Mitéran; Michel Paindavoine; Sebastien Bouillant (ICASSP, 2002)

Real Time Image Rotation Using Dynamic Reconfiguration. - El-Bay Bourennane; Claude Milan; Michel Paindavoine; Sophie Bouchoux (Real Time Imaging, 2002)

Generalization of Canny-Deriche filter for detection of noisy exponential edge. - El-Bay Bourennane; Pierre Gouton; Michel Paindavoine; Frédéric Truchetet (Signal Process., 2002)

Classification Boundary Approximation by Using Combination of Training Steps for Real-Time Image Segmentation. - Johel Mitéran; Sebastien Bouillant; El-Bay Bourennane (MLDM, 2003)

SVM approximation for real-time image segmentation by using an improved hyperrectangles-based method. - Johel Mitéran; Sebastien Bouillant; El-Bay Bourennane (Real Time Imaging, 2003)

Boosting: From data to hardware using automatic implementation tool. - Johel Mitéran; Jiri Matas; Julien Dubois; El-Bay Bourennane (EUSIPCO, 2004)

Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA. - Sophie Bouchoux; El-Bay Bourennane; Michel Paindavoine (ICIP, 2004)

Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA. - Sophie Bouchoux; El-Bay Bourennane; Johel Mitéran; Michel Paindavoine (ISVLSI, 2004)

Hardware implementation of content based video indexing algorithms. - Abdessalem Ben Abdelali; Abdellatif Mtibaa; El-Bay Bourennane; Mohamed Abid (ICECS, 2005)

STARSoC : A C-based platform for rapid prototyping of embedded system. - AbdelHalim Samahi; Sami Boukhechem; El-Bay Bourennane; Nasser E. Idirene (ReCoSoC, 2005)

Automatic Hardware Implementation Tool for a Discrete Adaboost-Based Decision Algorithm. - Johel Mitéran; Jiri Matas; El-Bay Bourennane; Michel Paindavoine; Julien Dubois (EURASIP J. Adv. Signal Process., 2005)

A closed form solution for the blind separation of two sources from two sensors using second order statistics. - Adel Belouchrani; El-Bey Bourennane; Karim Abed-Meraim (EUSIPCO, 2006)

Communication Interface Generation For HW/SW Architecture In The STARSoC Environment. - AbdelHalim Samahi; El-Bay Bourennane; Sami Boukhechem (ReConFig, 2006)

Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform. - AbdelHalim Samahi; El-Bay Bourennane (AHS, 2007)

TLM Platform Based on SystemC for STARSoC Design Space Exploration. - Sami Boukhechem; El-Bay Bourennane (AHS, 2008)

TLMCO-simulation for an open source MPSOC platform under STARSoC environment. - Sami Boukhechem; El-Bay Bourennane (SoC, 2008)

SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication. - Sami Boukhechem; El-Bay Bourennane (Int. J. Reconfigurable Comput., 2008)

Modeling and Verification of Dynamic Behavior in UML Models: A Graph Transformation Approach. - Elhillali Kerkouche; Allaoua Chaoui; El-Bay Bourennane; Ouassila Labbani (SEDE, 2009)

Memory requirements and simulation platform for the implementation of the H.264 encoder modules. - Kamel Messaoudi; El-Bay Bourennane; Salah Toumi; Elhillali Kerkouche; Ouassila Labbani (IPTA, 2010)

Towards Hardware implementation of video applications in new telecommunications devices - Lamjed Touil; Abdessalem Ben Abdelali; Abdellatif Mtibaa; El-Bey Bourennane (CoRR, 2010)

A UML and Colored Petri Nets Integrated Modeling and Analysis Approach using Graph Transformation. - Elhillali Kerkouche; Allaoua Chaoui; El-Bay Bourennane; Ouassila Labbani (J. Object Technol., 2010)

On the Use of Graph Transformation in the Modeling and Verification of Dynamic Behavior in UML Models. - Elhillali Kerkouche; Allaoua Chaoui; El-Bay Bourennane; Ouassila Labbani (J. Softw., 2010)

High-level modelling and automatic generation of dynamicaly reconfigurable systems. - Gilberto Ochoa; El-Bay Bourennane; Hassan Rabah; Ouassila Labbani (DASIP, 2011)

IP-XACT and marte based approach for partially reconfigurable systems-on-chip. - Gilberto Ochoa; El-Bay Bourennane; Ouassila Labbani; Kamel Messaoudi (FDL, 2011)

An FPGA based soft multiprocessor for DNS/DNSSEC authoritative server. - Rabah Sadoun; Adel Belouchrani; El-Bey Bourennane; Ahmed Zerguerras (Microprocess. Microsystems, 2011)

Model-Driven Approach for Automatic Dynamic Partially Reconfigurable IP Customization. - Gilberto Ochoa; Ouassila Labbani; El-Bay Bourennane; Philippe Soulard (IPDPS Workshops, 2012)

Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. - Gilberto Ochoa-Ruiz; Ouassila Labbani-Narsis; El-Bay Bourennane; Sana Cherif; Samy Meftali; Jean-Luc Dekeyser (ReConFig, 2012)

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. - Gilberto Ochoa-Ruiz; Ouassila Labbani; El-Bay Bourennane; Sana Cherif; Samy Meftali; Jean-Luc Dekeyser (RSP, 2012)

A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile. - Gilberto Ochoa-Ruiz; Ouassila Labbani; El-Bay Bourennane; Philippe Soulard; Sana Cherif (Des. Autom. Embed. Syst., 2012)

A novel methodology for accelerating bitstream relocation in partially reconfigurable systems. - Maamar Touiza; Gilberto Ochoa-Ruiz; El-Bay Bourennane; Abderrezak Guessoum; Kamel Messaoudi (Microprocess. Microsystems, 2013)

Implementation of universal digital architecture using 3D-NoC for mobile terminal. - Atef Benhaoues; El-Bay Bourennane; Camel Tanougast; Hichem Mayache; Salah Toumi; Kamel Messaoudi (CoDIT, 2014)

Hardware implementation for a new design of the VBSME Used in H.264/AVC. - Amira Yahi; Kamel Messaoudi; Salah Toumi; El-Bey Bourennane (CoDIT, 2014)

A Novel Architecture for Inter-FPGA Traffic Collision Management. - Atef Dorai; Virginie Fresse; El-Bay Bourennane; Abdellatif Mtibaa (CSE, 2014)

Ontology and protocol secure for SCADA. - Nabil Sahli; Mohamed Benmohammed; El-Bay Bourennane (Int. J. Metadata Semant. Ontologies, 2014)

Differentiated service for NoC-based multimedia applications. - Atef Dorai; Virginie Fresse; El-Bay Bourennane; Abdellatif Mtibaa (ICM, 2015)

A novel hardware accelerator for the HEVC intra prediction. - Farouk Amish; El-Bay Bourennane (NEWCAS, 2015)

Utilisation of the Array-OL specification language for self-generation of a memory controller especially for the H.264/AVC. - Kamel Messaoudi; El-Bay Bourennane; Salah Toumi; Hichem Mayache; Nawfel Messaoudi; Ouassila Labbani (Int. J. Embed. Syst., 2015)

Versatile digital architecture for mobile terminal. - Atef Benhaoues; Salah Toumi; Camel Tanougast; El-Bay Bourennane; Kamel Messaoudi; Hichem Mayache (Microprocess. Microsystems, 2015)

Connection of H.264/AVC hardware IPs using a specific Networks-on-Chip. - Kamel Messaoudi; Hichem Mayache; Atef Benhaoues; El-Bay Bourennane; Salah Toumi (Microprocess. Microsystems, 2015)

An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems. - Gilberto Ochoa-Ruiz; Sébastien Guillet; Florent de Lamotte; Éric Rutten; El-Bay Bourennane; Jean-Philippe Diguet; Guy Gogniat (ACM Trans. Design Autom. Electr. Syst., 2015)

Fast oriented Anisotropic Diffusion filter. - Amira Hadj Fredj; Jihene Malek; El-Bey Bourennane (IDT, 2016)

NoC Based Virtualized Accelerators for Cloud Computing. - Hiliwi Leake Kidane; El-Bay Bourennane; Gilberto Ochoa-Ruiz (MCSoC, 2016)

A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC. - Amira Yahi; Salah Toumi; El-Bay Bourennane; Kamel Messaoudi (Evol. Syst., 2016)

Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction. - Farouk Amish; El-Bay Bourennane (J. Syst. Archit., 2016)

Run-Time Scalable NoC for FPGA Based Virtualized IPs. - Hiliwi Leake Kidane; El-Bay Bourennane; Gilberto Ochoa-Ruiz (MCSoC, 2017)

Dynamic management of a partial reconfigurable hardware architecture for pedestrian detection in regions of interest. - Metzli Ramirez-Martinez; Francisco Sanchez-Fernandez; Philippe Brunet; Sidi Mohammed Senouci; El-Bay Bourennane (ReConFig, 2017)

A collision management structure for NoC deployment on multi-FPGA. - Atef Dorai; Virginie Fresse; Catherine Combes; El-Bay Bourennane; Abdellatif Mtibaa (Microprocess. Microsystems, 2017)

An Efficient FPGA Implementation of Anisotropic Diffusion Function for Medical Images. - Amira Hadj Fredj; Jihene Malek; El-Bay Bourennane (SSD, 2018)

Run-time Reconfigurable Network-On-Chip: A Survey. - Hiliwi Leake Kidane; El-Bay Bourennane (SSD, 2018)

MARTE and IP-XACT Based Approach for Run-Time Scalable NoC. - Hiliwi Leake Kidane; El-Bay Bourennane (MCSoC, 2018)

Implementation of Real Time Reconfigurable Embedded Architecture for People Counting in a Crowd Area. - Songchenchen Gong; El-Bay Bourennane (MISC, 2018)

A Graphical Modelling Editor for STARSoC Design Flow Tool Based on Model Driven Engineering Approach. - Elhillali Kerkouche; El-Bay Bourennane; Allaoua Chaoui (e Informatica Softw. Eng. J., 2018)

A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip. - Gilberto Ochoa-Ruiz; Pamela Wattebled; Maamar Touiza; Florent de Lamotte; El-Bay Bourennane; Samy Meftali; Jean-Luc Dekeyser; Jean-Philippe Diguet (J. Parallel Distributed Comput., 2018)

AODVCS, a new bio-inspired routing protocol based on cuckoo search algorithm for mobile ad hoc networks. - Akram Kout; Said Labed; Salim Chikhi; El-Bay Bourennane (Wirel. Networks, 2018)

Simulation Study of Video Transmission by Optical Fiber. - Nadira Boukhatem; Salah Toumi; El-Bey Bourennane; Abdelghani Redjati; Abderraouf Fares (CITSC, 2019)

Carbon monoxide detection: an IoT application used as a tool for civil protection services to save lives. - Badreddine Miles; Salim Chikhi; El-Bay Bourennane (ICFNDS, 2019)

Improving Video Object Detection by Seq-Bbox Matching. - Hatem Belhassen; Heng Zhang; Virginie Fresse; El-Bay Bourennane (VISIGRAPP (5: VISAPP), 2019)

The analysis of unreliable M[X]/G/1 queuing system with loss, vacation and two delays of verification. - Hafida Saggou; Ines Sadeg; Megdouda Ourbih-Tari; El-Bay Bourennane (Commun. Stat. Simul. Comput., 2019)

Adaptive neuro-fuzzy inference system based maximum power point tracking for stand-alone photovoltaic system. - Karima Amara; Ali Malek; Toufik Bakir; Arezki Fekik; Ahmad Taher Azar; Khaled Mohamad Almustafa; El-Bay Bourennane; Dallila Hocine (Int. J. Model. Identif. Control., 2019)

Palmprint identification performance improvement via patch-based binarized statistical image features. - Salim Bendjoudi; Hocine Bourouba; Hakim Doghmane; Kamel Messaoudi; El-Bay Bourennane (J. Electronic Imaging, 2019)

Palmprint identification performance improvement via patch-based binarized statistical image features (Erratum). - Salim Bendjoudi; Hocine Bourouba; Hakim Doghmane; Kamel Messaoudi; El-Bay Bourennane (J. Electronic Imaging, 2019)

An efficient hardware solution for 3D-HEVC intra-prediction. - Farouk Amish; El-Bay Bourennane (J. Real Time Image Process., 2019)

Multi-feature Counting of Dense Crowd Image Based on Multi-column Convolutional Neural Network. - Songchenchen Gong; El-Bay Bourennane; Junyu Gao 001 (ICCCS, 2020)

Artificial Intelligence and Cyber Security: Protecting and Maintaining Industry 4.0 Power Networks. - Nabil Sahli; Mohamed Benmohammed; Hugues Bersini; El-Bay Bourennane (IAM, 2020)

Towards General Purpose Object Detection: Deep Dense Grid Based Object Detection. - Solomon Negussie Tesema; El-Bay Bourennane (IIT, 2020)

A study of LoRaWAN protocol performance for IoT applications in smart agriculture. - Badreddine Miles; El-Bay Bourennane; Samia Boucherkha; Salim Chikhi (Comput. Commun., 2020)

Revisiting the High-Performance Reconfigurable Computing for Future Datacenters. - Qaiser Ijaz; El-Bay Bourennane; Ali Kashif Bashir; Hira Asghar (Future Internet, 2020)

Multimodal biometric recognition systems using deep learning based on the finger vein and finger knuckle print fusion. - Sara Daas; Amira Yahi; Toufik Bakir; Mouna Sedhane; Mohamed Boughazi; El-Bay Bourennane (IET Image Process., 2020)

Ear recognition based on discriminant multi-resolution image representation. - Hakim Doghmane; Hocine Bourouba; Kamel Messaoudi; El-Bay Bourennane (Int. J. Biom., 2020)

Multi-Grid Redundant Bounding Box Annotation for Accurate Object Detection. - Solomon Negussie Tesema; El-Bay Bourennane (DASC/PiCom/CBDCom/CyberSciTech, 2021)

A dynamic multi-sink routing protocol for static and mobile self-organizing wireless networks: A routing protocol for Internet of Things. - Mohamed Skander Daas; Salim Chikhi; El-Bay Bourennane (Ad Hoc Networks, 2021)

A Service-Oriented Component-Based Framework for Dynamic Reconfiguration Modeling Targeting SystemC/TLM. - Khaled Allem; El-Bay Bourennane; Youcef Khelfaoui (Int. J. Reconfigurable Comput., 2021)

High-performance hardware architecture of a robust block-cipher algorithm based on different chaotic maps and DNA sequence encoding. - Rim Amdouni; Mohamed Gafsi; Ramzi Guesmi; Mohamed Ali Hajjaji; Abdellatif Mtibaa; El-Bay Bourennane (Integr., 2022)

Hardware implementation of a strong pseudorandom number generator based block-cipher system for color image encryption and decryption. - Mohamed Gafsi; Rim Amdouni; Mohamed Ali Hajjaji; Abdellatif Mtibaa; El-Bey Bourennane (Int. J. Circuit Theory Appl., 2023)

FPGA Implementation of AES-Based on Optimized Dynamic s-Box. - Calvo Mayaudón Haroldo; Nakojah Chris David; Mahdi Madani; El-Bay Bourennane (SECRYPT, 2024)

HTC-retina: A hybrid retinal diseases classification model using transformer-Convolutional Neural Network from optical coherence tomography images. - Ayoub Laouarem; Chafia Kara-Mohamed; El-Bay Bourennane; Aboubekeur Hamdi-Cherif (Comput. Biol. Medicine, 2024)

JILDYA-Net: An Efficient Lightweight Multi-Class Classification Architecture for Skin Lesions. - Ayoub Laouarem; Chafia Kara-Mohamed; El-Bay Bourennane; Aboubekeur Hamdi-Cherif (Int. J. Imaging Syst. Technol., 2025)

Design and FPGA implementation of a novel cryptographic secure pseudo random number generator based on artificial neural networks and chaotic systems. - Youcef Alloun; Abdenour Kifouche; Mohamed Salah Azzaz; Mahdi Madani; El-Bay Bourennane; Said Sadoudi (Integr., 2025)

Visually Image Encryption and Compression Using a CNN-Based Auto Encoder. - Mahdi Madani; El-Bay Bourennane (CoRR, 2025)

Hardware implementation of a novel chaos-based cryptosystem for secure image transmission. - Rim Amdouni; Mahdi Madani; Mohamed Ali Hajjaji; El-Bay Bourennane; Mohamed Atri (Integr., 2026)