An approach to high-level synthesis system validation using formally verified transformations. - Rajesh Radhakrishnan; Elena Teica; Ranga Vemuri (HLDVT, 2000)

Verification of Basic Block Schedules Using RTL Transformations. - Rajesh Radhakrishnan; Elena Teica; Ranga Vemuri (CHARME, 2001)

On the verification of synthesized designs using automatically generated transformational witnesses. - Elena Teica; Rajesh Radhakrishnan; Ranga Vemuri (DATE, 2001)

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. - Naren Narasimhan; Elena Teica; Rajesh Radhakrishnan; Sriram Govindarajan; Ranga Vemuri (Formal Methods Syst. Des., 2001)