Designing a RISC CPU in Reversible Logic. - Robert Wille; Mathias Soeken; Daniel Große; Eleonora Schönborn; Rolf Drechsler (MBMV, 2011)

Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. - Robert Wille; Mathias Soeken; Eleonora Schönborn; Rolf Drechsler (ISVLSI, 2012)

Optimizing DD-based synthesis of reversible circuits using negative control lines. - Eleonora Schönborn; Kamalika Datta; Robert Wille; Indranil Sengupta 001; Hafizur Rahaman 001; Rolf Drechsler (DDECS, 2014)

RevVis: Visualization of Structures and Properties in Reversible Circuits. - Robert Wille; Jannis Stoppe; Eleonora Schönborn; Kamalika Datta; Rolf Drechsler (RC, 2014)

Design and Synthesis of Reversible Circuits using Hardware Description Languages. - Eleonora Schönborn; Rolf Drechsler (SyDe Summer School, 2015)

BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits. - Eleonora Schönborn; Kamalika Datta; Robert Wille; Indranil Sengupta 001; Hafizur Rahaman 001; Rolf Drechsler (VLSID, 2015)

SyReC: A hardware description language for the specification and synthesis of reversible circuits. - Robert Wille; Eleonora Schönborn; Mathias Soeken; Rolf Drechsler (Integr., 2016)

Scalable Design and Synthesis of Reversible Circuits. - Eleonora Schönborn (2016)