Inversion optimization in Majority-Inverter Graphs. - Eleonora Testa; Mathias Soeken; Odysseas Zografos; Luca Gaetano Amarù; Praveen Raghavan; Rudy Lauwereins; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (NANOARCH, 2016)

Multi-level logic benchmarks: An exactness study. - Luca Gaetano Amarù; Mathias Soeken; Winston Haaswijk; Eleonora Testa; Patrick Vuillod; Jiong Luo; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2017)

Wave pipelining for majority-based beyond-CMOS technologies. - Odysseas Zografos; A. De Meester; Eleonora Testa; Mathias Soeken; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Luca Gaetano Amarù; Praveen Raghavan; Francky Catthoor; Rudy Lauwereins (DATE, 2017)

Classifying Functions with Exact Synthesis. - Winston Haaswijk; Eleonora Testa; Mathias Soeken; Giovanni De Micheli (ISMVL, 2017)

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies. - Eleonora Testa; Odysseas Zografos; Mathias Soeken; Adrien Vaysset; Mauricio Manfrini; Rudy Lauwereins; Giovanni De Micheli (ISVLSI, 2017)

Practical exact synthesis. - Mathias Soeken; Winston Haaswijk; Eleonora Testa; Alan Mishchenko; Luca Gaetano Amarù; Robert K. Brayton; Giovanni De Micheli (DATE, 2018)

Majority logic synthesis. - Luca G. Amarù; Eleonora Testa; Miguel Couceiro; Odysseas Zografos; Giovanni De Micheli; Mathias Soeken (ICCAD, 2018)

Size Optimization of MIGs with an Application to QCA and STMG Technologies. - Heinz Riener; Eleonora Testa; Luca G. Amarù; Mathias Soeken; Giovanni De Micheli (NANOARCH, 2018)

Pairs of majority-decomposing functions. - Mathias Soeken; Eleonora Testa; Alan Mishchenko; Giovanni De Micheli (Inf. Process. Lett., 2018)

Scalable Generic Logic Synthesis: One Approach to Rule Them All. - Heinz Riener; Eleonora Testa; Winston Haaswijk; Alan Mishchenko; Luca G. Amarù; Giovanni De Micheli; Mathias Soeken (DAC, 2019)

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications. - Eleonora Testa; Mathias Soeken; Luca G. Amarù; Giovanni De Micheli (DAC, 2019)

Scalable Boolean Methods in a Modern Synthesis Flow. - Eleonora Testa; Luca G. Amarù; Mathias Soeken; Alan Mishchenko; Patrick Vuillod; Jiong Luo; Christopher Casares; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2019)

Logic Optimization of Majority-Inverter Graphs. - Heinz Riener; Eleonora Testa; Winston Haaswijk; Alan Mishchenko; Luca G. Amarù; Giovanni De Micheli; Mathias Soeken (MBMV, 2019)

A Hybrid Method for Spectral Translation Equivalent Boolean Functions. - Mathias Soeken; Eleonora Testa; D. Michael Miller (PACRIM, 2019)

Logic Synthesis for Established and Emerging Computing. - Eleonora Testa; Mathias Soeken; Luca Gaetano Amarù; Giovanni De Micheli (Proc. IEEE, 2019)

Mapping Monotone Boolean Functions into Majority. - Eleonora Testa; Mathias Soeken; Luca Gaetano Amarù; Winston Haaswijk; Giovanni De Micheli (IEEE Trans. Computers, 2019)

SAT-Sweeping Enhanced for Logic Synthesis. - Luca G. Amarù; Felipe S. Marranghello; Eleonora Testa; Christopher Casares; Vinicius N. Possani; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2020)

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). - Eleonora Testa; Samantha Lubaba Noor; Odysseas Zografos; Mathias Soeken; Francky Catthoor; Azad Naeemi; Giovanni De Micheli (DATE, 2020)

Extending Boolean Methods for Scalable Logic Synthesis. - Eleonora Testa; Luca G. Amarù; Mathias Soeken; Alan Mishchenko; Patrick Vuillod; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Access, 2020)

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. - Eleonora Testa; Mathias Soeken; Heinz Riener; Luca G. Amarù; Giovanni De Micheli (IACR Cryptol. ePrint Arch., 2020)

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies. - Eleonora Testa (2020)

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. - Eleonora Testa; Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (ASP-DAC, 2021)

LUT-Based Optimization For ASIC Design Flow. - Luca Gaetano Amarù; Vinicius N. Possani; Eleonora Testa; Felipe S. Marranghello; Christopher Casares; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2021)

Three-Input Gates for Logic Synthesis. - Dewmini Sudara Marakkalage; Eleonora Testa; Heinz Riener; Alan Mishchenko; Mathias Soeken; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Scalable Sequential Optimization Under Observability Don't Cares. - Dewmini Sudara Marakkalage; Eleonora Testa; Walter Lau Neto; Alan Mishchenko; Giovanni De Micheli; Luca G. Amarù (DATE, 2024)