Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates. - Elham Cheshmikhani; Hamid R. Zarandi (Microelectron. Reliab., 2015)

Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches. - Elham Cheshmikhani; Amir Mahdi Hosseini Monazzah; Hamed Farbeh; Seyed Ghassem Miremadi (EDCC, 2016)

Accelerating Dynamic Fault Tree Analysis Based on Stochastic Logic Utilizing GPGPUs. - Elham Cheshmikhani; Hamid R. Zarandi (PDP, 2016)

Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field-Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk. - Shahab Shoar; Hamid R. Zarandi; Farnad Nasirzadeh; Elham Cheshmikhani (Qual. Reliab. Eng. Int., 2017)

ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches. - Elham Cheshmikhani; Hamed Farbeh; Hossein Asadi 001 (ASP-DAC, 2019)

Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation. - Elham Cheshmikhani; Hamed Farbeh; Hossein Asadi 001 (DATE, 2019)

TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. - Elham Cheshmikhani; Hamed Farbeh; Seyed Ghassem Miremadi; Hossein Asadi 001 (IEEE Trans. Computers, 2019)

A-CACHE: Alternating Cache Allocation to Conduct Higher Endurance in NVM-Based Caches. - Hamed Farbeh; Amir Mahdi Hosseini Monazzah; Ensieh Aliagha; Elham Cheshmikhani (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation. - Mostafa Hadizadeh; Elham Cheshmikhani; Hossein Asadi 001 (DATE, 2020)

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. - Elham Cheshmikhani; Hamed Farbeh; Hossein Asadi 001 (IEEE Trans. Reliab., 2020)

A General Framework for Accelerator Management Based on ISA Extension. - Elham Cheshmikhani; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2022)

3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison. - Elham Cheshmikhani; Hamed Farbeh; Hossein Asadi 001 (IEEE Trans. Computers, 2022)

CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. - Mostafa Hadizadeh; Elham Cheshmikhani; Maysam Rahmanpour; Onur Mutlu; Hossein Asadi 001 (IEEE Trans. Parallel Distributed Syst., 2022)

IXIAM: ISA EXtension for Integrated Accelerator Management. - Biagio Peccerillo; Elham Cheshmikhani; Mirco Mannino; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2023)

Online Soft Error Tolerance in ReRAM Crossbars for Deep Learning Accelerators. - Benyamin Khezeli; Hamid R. Zarandi; Elham Cheshmikhani (CoRR, 2024)

A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression. - Elham Cheshmikhani; Fateme Shokouhinia; Hamed Farbeh (IEEE Trans. Circuits Syst. II Express Briefs, 2024)