An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits. - Elham K. Moghaddam; Shaahin Hessabi (ATS, 2007)

An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits. - Elham K. Moghaddam; Shaahin Hessabi (DSD, 2007)

Low capture power at-speed test in EDT environment. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Xijiang Lin; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2010)

At-speed scan test with low switching activity. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Mark Kassab (VTS, 2010)

Power Aware Embedded Test. - Xijiang Lin; Elham K. Moghaddam; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jerzy Tyszer (Asian Test Symposium, 2011)

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Jakub Janicki (Asian Test Symposium, 2011)

Low power compression utilizing clock-gating. - Janusz Rajski; Elham K. Moghaddam; Sudhakar M. Reddy (ITC, 2011)

Isometric test compression with low toggling activity. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (ITC, 2014)

Design for low test pattern counts. - Haluk Konuk; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Deepak Solanki; Jerzy Tyszer; Justyna Zawada (DAC, 2015)

Embedded deterministic test points for compact cell-aware tests. - Cesar Acero; Derek Feltham; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Marek Patyra; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2015)

Isometric Test Data Compression. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

On Test Points Enhancing Hardware Security. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ATS, 2016)

Minimal area test points for deterministic patterns. - Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Sudhakar M. Reddy; Janusz Rajski; Jerzy Tyszer (ITC, 2016)

Test point insertion in hybrid test compression/LBIST architectures. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2016)

On New Test Points for Compact Cell-Aware Tests. - Cesar Acero; Derek Feltham; Marek Patyra; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Des. Test, 2016)

Embedded Deterministic Test Points. - Cesar Acero; Derek Feltham; Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Marek Patyra; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Hardware Protection via Logic Locking Test Points. - Michael Chen; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Test Time and Area Optimized BrST Scheme for Automotive ICs. - Nilanjan Mukherjee 001; Jerzy Tyszer; Daniel Tille; Mahendar Sapati; Yingdi Liu; Jeffrey Mayer; Sylwester Milewski; Elham K. Moghaddam; Janusz Rajski; Jedrzej Solecki (ITC, 2019)

Logic BIST With Capture-Per-Clock Hybrid Test Points. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Time and Area Optimized Testing of Automotive ICs. - Nilanjan Mukherjee 001; Daniel Tille; Mahendar Sapati; Yingdi Liu; Jeffrey Mayer; Sylwester Milewski; Elham K. Moghaddam; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2021)