Scheduling memory accesses through a shared bus. - Eli Almog; Hadas Shachnai (Perform. Evaluation, 2001)

Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification. - Allon Adir; Eli Almog; Laurent Fournier; Eitan Marcus; Michal Rimon; Michael Vinov; Avi Ziv (IEEE Des. Test Comput., 2004)

Facing the challenge of new design features: an effective verification approach. - Wisam Kadry; Ronny Morad; Alex Goryachev; Eli Almog; Christopher A. Krygowski (DAC, 2011)

Key advances in the presilicon functional verification of the IBM zEnterprise microprocessor and storage hierarchy. - Christopher A. Krygowski; Eli Almog; Dean G. Bair; Raimund Breil; Gero Dittmann; Rebecca M. Gott; William J. Lewis; Alia D. Shah; Brian W. Thompto (IBM J. Res. Dev., 2012)

A Computational Design Tool for Gradual Transition of Knit Structures in Seamless Circular Knitting. - Yoav Sterman; Eli Almog (Comput. Aided Des., 2022)