A Connection Router for the Dynamic Reconfiguration of FPGAs. - Elias Vansteenkiste; Karel Bruneel; Dirk Stroobandt (ARC, 2012)

Maximizing the reuse of routing resources in a reconfiguration-aware connection router. - Elias Vansteenkiste; Karel Bruneel; Dirk Stroobandt (FPL, 2012)

Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS. - Karel Heyse; Tom Davidson; Elias Vansteenkiste; Karel Bruneel; Dirk Stroobandt (FPL, 2013)

A connection-based router for FPGAs. - Elias Vansteenkiste; Karel Bruneel; Dirk Stroobandt (FPT, 2013)

A novel tool flow for increased routing configuration similarity in multi-mode circuits. - Brahim Al Farisi; Elias Vansteenkiste; Karel Bruneel; Dirk Stroobandt (ISVLSI, 2013)

Parameterised FPGA reconfigurations for efficient test set generation. - Alexandra Kourfali; Elias Vansteenkiste; Dirk Stroobandt (ReConFig, 2014)

TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network. - Elias Vansteenkiste; Brahim Al Farisi; Karel Bruneel; Dirk Stroobandt (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing. - Catalin Bogdan Ciobanu; Ana Lucia Varbanescu; Dionisios N. Pnevmatikatos; George Charitopoulos; Xinyu Niu; Wayne Luk; Marco D. Santambrogio; Donatella Sciuto; Muhammed Al Kadi; Michael Hübner 001; Tobias Becker; Georgi Gaydadjiev; et al. (CSE, 2015)

Logic Gates in the routing network of FPGAs (Abstract Only). - Elias Vansteenkiste; Berg Severens; Dirk Stroobandt (FPGA, 2015)

Estimating circuit delays in FPGAs after technology mapping. - Berg Severens; Elias Vansteenkiste; Karel Heyse; Dirk Stroobandt (FPL, 2015)

Analyzing the divide between FPGA academic and commercial results. - Elias Vansteenkiste; Alireza Kaviani; Henri Fraisse (FPT, 2015)

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. - Dionisios N. Pnevmatikatos; Kyprianos Papadimitriou; Tobias Becker; Peter Böhm; Andreas Brokalakis; Karel Bruneel; Catalin Bogdan Ciobanu; Tom Davidson; Georgi Gaydadjiev; Karel Heyse; Wayne Luk; Xinyu Niu; et al. (Microprocess. Microsystems, 2015)

Identification of Dynamic Circuit Specialization Opportunities in RTL Code. - Tom Davidson; Elias Vansteenkiste; Karel Heyse; Karel Bruneel; Dirk Stroobandt (ACM Trans. Reconfigurable Technol. Syst., 2015)

Liquid: Fast placement prototyping through steepest gradient descent movement. - Elias Vansteenkiste; Seppe Lenders; Dirk Stroobandt (FPL, 2016)

Runtime-quality tradeoff in partitioning based multithreaded packing. - Dries Vercruyce; Elias Vansteenkiste; Dirk Stroobandt (FPL, 2016)

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications. - Amit Kulkarni 002; Elias Vansteenkiste; Dirk Stroobandt; Andreas Brokalakis; Antonis Nikitakis (IPDPS Workshops, 2016)

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures. - Dirk Stroobandt; Ana Lucia Varbanescu; Catalin Bogdan Ciobanu; Muhammed Al Kadi; Andreas Brokalakis; George Charitopoulos; Tim Todman; Xinyu Niu; Dionisios N. Pnevmatikatos; Amit Kulkarni 002; Elias Vansteenkiste; Wayne Luk; et al. (ReCoSoC, 2016)

Liquid: High quality scalable placement for large heterogeneous FPGAs. - Dries Vercruyce; Elias Vansteenkiste; Dirk Stroobandt (FPT, 2017)

Taming Adversarial Domain Transfer with Structural Constraints for Image Enhancement. - Elias Vansteenkiste; Patrick Kern (CoRR, 2017)

Hierarchical Force-Based Block Spreading for Analytical FPGA Placement. - Dries Vercruyce; Elias Vansteenkiste; Dirk Stroobandt (FPL, 2018)

How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance. - Dries Vercruyce; Elias Vansteenkiste; Dirk Stroobandt (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router. - Dries Vercruyce; Elias Vansteenkiste; Dirk Stroobandt (FCCM, 2019)