Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge. - Efi Rotem; Alon Naveh; Doron Rajwan; Avinash Ananthakrishnan; Eliezer Weissmann (Hot Chips Symposium, 2011)

Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge. - Efraim Rotem; Alon Naveh; Avinash Ananthakrishnan; Eliezer Weissmann; Doron Rajwan (IEEE Micro, 2012)

H-EARtH: Heterogeneous Multicore Platform Energy Management. - Efraim Rotem; Uri C. Weiser; Avi Mendelson; Ran Ginosar; Eliezer Weissmann; Yoni Aizik (Computer, 2016)

Alder Lake Architecture. - Efraim Rotem; Yuli Mandelblat; Vadim Basin; Eliezer Weissmann; Arik Gihon; Rajshree Chabukswar; Russ Fenger; Monica Gupta (HCS, 2021)

Intel Alder Lake CPU Architectures. - Efraim Rotem; Adi Yoaz; Lihu Rappoport; Stephen J. Robinson; Julius Yuli Mandelblat; Arik Gihon; Eliezer Weissmann; Rajshree Chabukswar; Vadim Basin; Russell Fenger; Monica Gupta; Ahmad Yasin (IEEE Micro, 2022)