Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology. - Weiwu Hu; Ji-Ye Zhao; Shi-Qiang Zhong; Xu Yang; Elio Guidetti; Chris Wu (J. Comput. Sci. Technol., 2007)

A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing. - Giuseppe Notarangelo; Francesco Pappalardo 002; Elena Salurso; Elio Guidetti (J. Low Power Electron., 2007)

An Ultra-Low Power Data Aggregation System for Wireless Micro Sensor Networks. - Giuseppe Visalli; Elio Guidetti (J. Low Power Electron., 2007)

A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip. - Nathan Ickes; Yildiz Sinangil; Francesco Pappalardo 002; Elio Guidetti; Anantha P. Chandrakasan (ESSCIRC, 2011)

A 14-bit extended-range incremental ΣΔ ADC matlab-model based on 90nm CMOS-technology. - Domenico M. Cavallo; Marcello De Matteis; Marco Ronchi; Elio Guidetti; Giuseppina Leggeri; Andrea Baschirotto (ICICDT, 2013)

The Orlando Project: A 28 nm FD-SOI Low Memory Embedded Neural Network ASIC. - Giuseppe Desoli; Valeria Tomaselli; Emanuele Plebani; Giulio Urlini; Danilo Pau; Viviana D'Alto; Tommaso Majo; Fabio De Ambroggi; Thomas Boesch; Surinder Pal Singh; Elio Guidetti; Nitin Chawla (ACIVS, 2016)

14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems. - Giuseppe Desoli; Nitin Chawla; Thomas Boesch; Surinder Pal Singh; Elio Guidetti; Fabio De Ambroggi; Tommaso Majo; Paolo Zambotti; Manuj Ayodhyawasi; Harvinder Singh; Nalin Aggarwal (ISSCC, 2017)

An Integrated Low-power 802.11ba Wake-up Radio for IoT with Embedded Microprocessor. - Marco Ronchi; Francesco Malena; Michele Caselli; Devis Gatti; Ermano Picco; Elena Salurso; Marco Sosio; Lucio Ticli; Alessandro Tomasoni; Eusebio Di-Cola; Tommaso Majo; Fabio Osnato; et al. (ICECS 2022, 2022)

Design-Space Exploration of Integrated Frequency Synthesis Architecture for Wake-Up Radio in Low-Power Wi-Fi Applications. - V. Paoli; M. Mestice; S. Saponara; Marco Ronchi; Elio Guidetti; Fabio Osnato (ApplePies, 2024)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. - Riccardo Tedeschi; Gianmarco Ottavi; Côme Allart; Nils Wistoff; Zexin Fu; Filippo Grillotti; Fabio De Ambroggi; Elio Guidetti; Jean-Baptiste Rigaud; Olivier Potin; Jean-Roch Coulon; César Fuguet; et al. (CoRR, 2025)