Design of a Pipelined Radix 4 CORDIC Processor. - Javier D. Bruguera; Elisardo Antelo; Emilio L. Zapata (Parallel Comput., 1993)

Redundant CORDIC Rotator Based on Parallel Prediction. - Elisardo Antelo; Javier D. Bruguera; Julio Villalba; Emilio L. Zapata (IEEE Symposium on Computer Arithmetic, 1995)

Digit On-line Large Radix CORDIC Rotator. - Roberto R. Osorio; Elisardo Antelo; Javier D. Bruguera; Julio Villalba; Emilio L. Zapata (ASAP, 1995)

CORDIC Architectures with Parallel Compensation of the Scale Factor. - Julio Villalba; José Antonio Hidalgo López; Emilio L. Zapata; Elisardo Antelo; Javier D. Bruguera (ASAP, 1995)

Radix-4 Vectoring Cordic Algorithm And Architectures. - Julio Villalba; J. C. Arrabal; Emilio L. Zapata; Elisardo Antelo; Javier D. Bruguera (ASAP, 1996)

High Radix Cordic Rotation Based on Selection by Rounding. - Elisardo Antelo; Javier D. Bruguera; Tomás Lang; Julio Villalba; Emilio L. Zapata (Euro-Par, Vol. II, 1996)

Unified Mixed Radix 2-4 Redundant CORDIC Processor. - Elisardo Antelo; Javier D. Bruguera; Emilio L. Zapata (IEEE Trans. Computers, 1996)

CORDIC-based computation of arccos and arcsin. - Tomás Lang; Elisardo Antelo (ASAP, 1997)

Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. - Elisardo Antelo; Javier D. Bruguera; Tomás Lang; Emilio L. Zapata (IEEE Trans. Computers, 1997)

High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. - Elisardo Antelo; Julio Villalba; Javier D. Bruguera; Emilio L. Zapata (IEEE Trans. Computers, 1997)

Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. - Elisardo Antelo; Tomás Lang; Javier D. Bruguera (IEEE Trans. Computers, 1998)

CORDIC Vectoring with Arbitrary Target Value. - Tomás Lang; Elisardo Antelo (IEEE Trans. Computers, 1998)

A novel design of a two operand normalization circuit. - Elisardo Antelo; Montserrat Bóo; Javier D. Bruguera; Emilio L. Zapata (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Radix-4 Vectoring CORDIC Algorithm and Architectures. - Julio Villalba; Emilio L. Zapata; Elisardo Antelo; Javier D. Bruguera (J. VLSI Signal Process., 1998)

Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. - Elisardo Antelo; Tomás Lang; Javier D. Bruguera (IEEE Symposium on Computer Arithmetic, 1999)

Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. - Elisardo Antelo; Tomás Lang; Javier D. Bruguera (IEEE Trans. Computers, 2000)

Very-High Radix CORDIC Rotation Based on Selection by Rounding. - Elisardo Antelo; Tomás Lang; Javier D. Bruguera (J. VLSI Signal Process., 2000)

CORDIC-Based Computation of ArcCos. - Tomás Lang; Elisardo Antelo (J. VLSI Signal Process., 2000)

Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation. - Tomás Lang; Elisardo Antelo (IEEE Symposium on Computer Arithmetic, 2001)

Fast Radix-4 Retimed Division with Selection by Comparisons. - Elisardo Antelo; Tomás Lang; Paolo Montuschi; Alberto Nannarelli (ASAP, 2002)

Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root. - Tomás Lang; Elisardo Antelo (IEEE Trans. Computers, 2003)

Implementation of the Exponential Function in a Floating-Point Unit. - Álvaro Vázquez; Elisardo Antelo (J. VLSI Signal Process., 2003)

Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. - Elisardo Antelo; Tomás Lang; Paolo Montuschi; Alberto Nannarelli (IEEE Symposium on Computer Arithmetic, 2005)

Low Latency Pipelined Circular CORDIC. - Elisardo Antelo; Julio Villalba (IEEE Symposium on Computer Arithmetic, 2005)

Digit-Recurrence Dividers with Reduced Logical Depth. - Elisardo Antelo; Tomás Lang; Paolo Montuschi; Alberto Nannarelli (IEEE Trans. Computers, 2005)

High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics. - Tomás Lang; Elisardo Antelo (IEEE Trans. Computers, 2005)

A New Family of High.Performance Parallel Decimal Multipliers. - Álvaro Vázquez; Elisardo Antelo; Paolo Montuschi (IEEE Symposium on Computer Arithmetic, 2007)

A radix-10 SRT divider based on alternative BCD codings. - Álvaro Vázquez; Elisardo Antelo; Paolo Montuschi (ICCD, 2007)

New insights on Ling adders. - Álvaro Vázquez; Elisardo Antelo (ASAP, 2008)

A Low-Latency Pipelined 2D and 3D CORDIC Processors. - Elisardo Antelo; Julio Villalba; Emilio L. Zapata (IEEE Trans. Computers, 2008)

A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding. - Álvaro Vázquez; Elisardo Antelo (IEEE Symposium on Computer Arithmetic, 2009)

Computation of Decimal Transcendental Functions Using the CORDIC Algorithm. - Álvaro Vázquez; Julio Villalba; Elisardo Antelo (IEEE Symposium on Computer Arithmetic, 2009)

A Comment on "Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network". - Elisardo Antelo (IEEE Comput. Archit. Lett., 2009)

Improved Design of High-Performance Parallel Decimal Multipliers. - Álvaro Vázquez; Elisardo Antelo; Paolo Montuschi (IEEE Trans. Computers, 2010)

Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers. - Fabrizio Lamberti; Nikolaos Andrikos; Elisardo Antelo; Paolo Montuschi (IEEE Trans. Computers, 2011)

FlexSig: Implementing flexible hardware signatures. - Lois Orosa 001; Elisardo Antelo; Javier D. Bruguera (ACM Trans. Archit. Code Optim., 2012)

Guest Editors' Introduction: Special Section on Computer Arithmetic. - Elisardo Antelo; David Hough 001; Paolo Ienne (IEEE Trans. Computers, 2012)

Redundant Floating-Point Decimal CORDIC Algorithm. - Álvaro Vázquez; Julio Villalba-Moreno; Elisardo Antelo; Emilio L. Zapata (IEEE Trans. Computers, 2012)

Fast Radix-10 Multiplication Using Redundant BCD Codes. - Álvaro Vázquez; Elisardo Antelo; Javier D. Bruguera (IEEE Trans. Computers, 2014)

Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors. - Lois Orosa 001; Javier D. Bruguera; Elisardo Antelo (Comput. J., 2016)

A Number System Approach for Adder Topologies. - Álvaro Vázquez; Elisardo Antelo (ARITH, 2017)

A Sum Error Detection Scheme for Decimal Arithmetic. - Álvaro Vázquez; Elisardo Antelo (ARITH, 2017)

Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. - Elisardo Antelo; Paolo Montuschi; Alberto Nannarelli (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

New 3D Projection Transformation for Point Clouds. - Álvaro Vázquez; Elisardo Antelo (ARITH, 2019)

ENBB Processor: Towards the ExaScale Numerical Brain Box [Position Paper]. - Elisardo Antelo (CoRR, 2019)