Functional Verification of ECL Circuits Including Voltage Regulators. - Elizabeth J. Brauer; Sung-Mo Kang (ISCAS, 1993)

Estimating Node Voltages in Bipolar Circuits Using Linear Programming. - Elizabeth J. Brauer; Sung-Mo Kang (ISCAS, 1995)

An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations. - Elizabeth J. Brauer; Sung-Mo Kang (ISCAS, 1995)

An algorithm for functional verification of digital ECL circuits. - Elizabeth J. Brauer; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A Full-Swing Bootstrapped BiCMOS Buffer. - Elizabeth J. Brauer; Pradeep Elamanchili (Great Lakes Symposium on VLSI, 1997)

Analog Circuit Model of Lamprey Unit Pattern Generator. - Elizabeth J. Brauer; Ranu Jung; Denise M. Wilson; James J. Abbas (Great Lakes Symposium on VLSI, 1997)

Sensitivity analysis of an analog circuit model of lamprey unit pattern generator. - Elizabeth J. Brauer; Ranu Jung; Denise M. Wilson; James J. Abbas (ICNN, 1997)

Additive Decomposition Applied to the Semiconductor Drift-Diffusion Model. - Elizabeth J. Brauer; Marek Turowski; James M. McDonough (VLSI Design, 1998)

Hardware implementation of a neural network pattern shaper algorithm. - Elizabeth J. Brauer; James J. Abbas; Brian Callaway; Joshua Colvin; John Farris (IJCNN, 1999)

Low noise MCML prefix adders using 0.18 µm CMOS technology. - Elizabeth J. Brauer; Yusuf Leblebici (Circuits, Signals, and Systems, 2004)

Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. - Elizabeth J. Brauer; Yusuf Leblebici (Circuits, Signals, and Systems, 2004)

Finding efficient inductor geometries in digital CMOS process for RF applications. - Elizabeth J. Brauer; Vikram Magoon (Circuits, Signals, and Systems, 2004)

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. - Elizabeth J. Brauer; Ilhan Hatirnaz; Stéphane Badel; Yusuf Leblebici (ISCAS, 2006)

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. - Stéphane Badel; Ilhan Hatirnaz; Yusuf Leblebici; Elizabeth J. Brauer (VLSI-SoC, 2006)

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. - Armin Tajalli; Eric A. Vittoz; Yusuf Leblebici; Elizabeth J. Brauer (ESSCIRC, 2007)

Improving the power-delay product in SCL circuits using source follower output stage. - Armin Tajalli; Frank K. Gürkaynak; Yusuf Leblebici; Massimo Alioto; Elizabeth J. Brauer (ISCAS, 2008)

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. - Armin Tajalli; Massimo Alioto; Elizabeth J. Brauer; Yusuf Leblebici (PATMOS, 2008)

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. - Armin Tajalli; Elizabeth J. Brauer; Yusuf Leblebici; Eric A. Vittoz (IEEE J. Solid State Circuits, 2008)

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. - Armin Tajalli; Elizabeth J. Brauer; Yusuf Leblebici (Microelectron. J., 2009)