Methods for Reducing Events in Sequential Circuit Fault Simulation. - Elizabeth M. Rudnick; Thomas M. Niermann; Janak H. Patel (ICCAD, 1991)

Diagnostic Fault Simulation of Sequential Circuits. - Elizabeth M. Rudnick; W. Kent Fuchs; Janak H. Patel (ITC, 1992)

Probe point insertion for at-speed test. - Elizabeth M. Rudnick; Vivek Chickermane; Janak H. Patel (VTS, 1992)

Non-Scan Design-for-Testability Techniques for Sequential Circuits. - Vivek Chickermane; Elizabeth M. Rudnick; Prithviraj Banerjee; Janak H. Patel (DAC, 1993)

A Fast and Accurate Gate-Level Transient Fault Simulation Environment. - Hungse Cha; Elizabeth M. Rudnick; Gwan S. Choi; Janak H. Patel; Ravishankar K. Iyer (FTCS, 1993)

Sequential Circuit Test Generation in a Genetic Algorithm Framework. - Elizabeth M. Rudnick; Janak H. Patel; Gary S. Greenstein; Thomas M. Niermann (DAC, 1994)

Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. - Elizabeth M. Rudnick; John G. Holm; Daniel G. Saab; Janak H. Patel (EDAC-ETC-EUROASIC, 1994)

An observability enhancement approach for improved testability and at-speed test. - Elizabeth M. Rudnick; Vivek Chickermane; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. - Elizabeth M. Rudnick; Janak H. Patel (DAC, 1995)

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. - Srikanth Venkataraman; Ismed Hartanto; W. Kent Fuchs; Elizabeth M. Rudnick; Sreejit Chakravarty; Janak H. Patel (DAC, 1995)

A genetic approach to test application time reduction for full scan and partial scan circuits. - Elizabeth M. Rudnick; Janak H. Patel (VLSI Design, 1995)

Sequential circuit testability enhancement using a nonscan approach. - Elizabeth M. Rudnick; Vivek Chickermane; Prithviraj Banerjee; Janak H. Patel (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Alternating Strategies for Sequential Circuit ATPG. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ED&TC, 1996)

Enhancing high-level control-flow for improved testability. - Frank F. Hsu; Elizabeth M. Rudnick; Janak H. Patel (ICCAD, 1996)

Simulation-based techniques for dynamic test sequence compaction. - Elizabeth M. Rudnick; Janak H. Patel (ICCAD, 1996)

Testability Insertion in Behavioral Descriptions. - Frank F. Hsu; Elizabeth M. Rudnick; Janak H. Patel (ISSS, 1996)

On Potential Fault Detection in Sequential Circuits. - Elizabeth M. Rudnick; Janak H. Patel; Irith Pomeranz (ITC, 1996)

Automatic test generation using genetically-engineered distinguishing sequences. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1996)

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. - Terry Lee; Ibrahim N. Hajj; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1996)

A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. - Hungse Cha; Elizabeth M. Rudnick; Janak H. Patel; Ravishankar K. Iyer; Gwan S. Choi (IEEE Trans. Computers, 1996)

Sequential circuit test generation using dynamic state traversal. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ED&TC, 1997)

Effects of delay models on peak power estimation of VLSI sequential circuits. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ICCAD, 1997)

K2: an estimator for peak sustainable power of VLSI circuits. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ISLPED, 1997)

Putting the Squeeze on Test Sequences. - Elizabeth M. Rudnick; Janak H. Patel (ITC, 1997)

Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. - Dilip Krishnaswamy; Prithviraj Banerjee; Elizabeth M. Rudnick; Janak H. Patel (Workshop on Parallel and Distributed Simulation, 1997)

Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. - Charles R. Graham; Elizabeth M. Rudnick; Janak H. Patel (VLSI Design, 1997)

Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. - Dilip Krishnaswamy; Michael S. Hsiao; Vikram Saxena; Elizabeth M. Rudnick; Janak H. Patel; Prithviraj Banerjee (VLSI Design, 1997)

Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. - Elizabeth M. Rudnick; Janak H. Patel (VLSI Design, 1997)

Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1997)

SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. - Dilip Krishnaswamy; Elizabeth M. Rudnick; Janak H. Patel; Prithviraj Banerjee (VTS, 1997)

Static logic implication with application to redundancy identification. - Jian-Kun Zhao; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1997)

A genetic algorithm framework for test generation. - Elizabeth M. Rudnick; Janak H. Patel; Gary S. Greenstein; Thomas M. Niermann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. - Elizabeth M. Rudnick; Roberto Vietti; Akilah Ellis; Fulvio Corno; Paolo Prinetto; Matteo Sonza Reorda (DATE, 1998)

Enhancing topological ATPG with high-level information and symbolic techniques. - Fulvio Corno; Janak H. Patel; Elizabeth M. Rudnick; Matteo Sonza Reorda; Roberto Vietti (ICCD, 1998)

Partial Scan Selection Based on Dynamic Reachability and Observability Information. - Michael S. Hsiao; Gurjeet S. Saund; Elizabeth M. Rudnick; Janak H. Patel (VLSI Design, 1998)

Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. - Yanti Santoso; Matthew C. Merten; Elizabeth M. Rudnick; Miron Abramovici (DATE, 1999)

A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis. - Jue Wu; Gary S. Greenstein; Elizabeth M. Rudnick (DATE, 1999)

A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults. - Jue Wu; Elizabeth M. Rudnick (VLSI Design, 1999)

Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Computers, 1999)

Efficient Techniques for Dynamic Test Sequence Compaction. - Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Computers, 1999)

Microprocessor Design Verification. - Vikram Iyengar; Elizabeth M. Rudnick (The VLSI Handbook, 1999)

Diagnostic Testing of Embedded Memories Using BIST. - Timothy J. Bergfeld; Dirk Niggemeyer; Elizabeth M. Rudnick (DATE, 2000)

Combining symbolic and genetic techniques for efficient sequential circuit test generation. - Marco Boschini; Xiaoming Yu; Franco Fummi; Elizabeth M. Rudnick (ETW, 2000)

Diagnostic test generation for sequential circuits. - Xiaoming Yu; Jue Wu; Elizabeth M. Rudnick (ITC, 2000)

Diagnostic Testing of Embedded Memories Based on Output Tracing. - Dirk Niggemeyer; Elizabeth M. Rudnick; Michael Redeker (MTDT, 2000)

A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. - Ta-Chung Chang; Vikram Iyengar; Elizabeth M. Rudnick (J. Electron. Test., 2000)

Compact Test Generation Using a Frozen Clock Testing Strategy. - Elizabeth M. Rudnick; Miron Abramovici (J. Inf. Sci. Eng., 2000)

Bridge fault diagnosis using stuck-at fault simulation. - Jue Wu; Elizabeth M. Rudnick (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Dynamic state traversal for sequential circuit test generation. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ACM Trans. Design Autom. Electr. Syst., 2000)

Peak power estimation of VLSI circuits: new peak power measures. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A genetic approach to automatic bias generation for biased random instruction generation. - Mrinal Bose; Jongshin Shin; Elizabeth M. Rudnick; Todd Dukes; Magdy Abadir (CEC, 2001)

Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. - Mrinal Bose; Elizabeth M. Rudnick; Magdy S. Abadir (IOLTW, 2001)

At-speed logic BIST using a frozen clock testing strategy. - Jongshin Shin; Xiaoming Yu; Elizabeth M. Rudnick; Miron Abramovici (ITC, 2001)

Sequential ATPG Using Combinational Algorithms. - Miron Abramovici; Xiaoming Yu; Elizabeth M. Rudnick (LATW, 2001)

Automatic Generation of Diagnostic March Tests. - Dirk Niggemeyer; Elizabeth M. Rudnick (VTS, 2001)

Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach. - Franco Fummi; Marco Boschini; Xiaoming Yu; Elizabeth M. Rudnick (J. Electron. Test., 2001)

Use of a field programmable gate array for education in manufacturing test and automatic test equipment. - Dirk Niggemeyer; Kevin J. Stephano; Elizabeth M. Rudnick (IEEE Trans. Educ., 2001)

Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. - Ismed Hartanto; Srikanth Venkataraman; W. Kent Fuchs; Elizabeth M. Rudnick; Janak H. Patel; Sreejit Chakravarty (ACM Trans. Design Autom. Electr. Syst., 2001)

Low-cost sequential ATPG with clock-control DFT. - Miron Abramovici; Xiaoming Yu; Elizabeth M. Rudnick (DAC, 2002)

Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm. - Xiaoming Yu; Alessandro Fin; Franco Fummi; Elizabeth M. Rudnick (GECCO, 2002)

A Genetic Testing Framework for Digital Integrated Circuits. - Xiaoming Yu; Alessandro Fin; Franco Fummi; Elizabeth M. Rudnick (ICTAI, 2002)

A data acquisition methodology for on-chip repair of embedded memories. - Dirk Niggemeyer; Elizabeth M. Rudnick (ACM Trans. Design Autom. Electr. Syst., 2003)

Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing. - Dirk Niggemeyer; Elizabeth M. Rudnick (IEEE Trans. Computers, 2004)