Fast Test Cost Calculation for Hybrid BIST in Digital Systems. - Elmet Orasson; Rein Raidma; Raimund Ubar; Gert Jervan; Zebo Peng (DSD, 2001)

Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. - Gert Jervan; Helena Kruus; Elmet Orasson; Raimund Ubar (SIES, 2007)

Learning Digital Test and Diagnostics via Internet. - Raimund Ubar; Artur Jutman; Margus Kruus; Elmet Orasson; Sergei Devadze; Heinz-Dietrich Wuttke (Int. J. Online Eng., 2007)

Hybrid BIST optimization using reseeding and test set compaction. - Gert Jervan; Elmet Orasson; Helena Kruus; Raimund Ubar (Microprocess. Microsystems, 2008)

Functional Built-In Self-Test for processor cores in SoC. - Raimund Ubar; Viljar Indus; Oliver Kalmend; Teet Evartson; Elmet Orasson (NORCHIP, 2012)

Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. - Raimund Ubar; Lembit Jurimagi; Elmet Orasson; Galina Josifovska; Stephen Adeboye Oyeniran (DSD, 2015)

Scalable algorithm for structural fault collapsing in digital circuits. - Raimund Ubar; Lembit Jurimagi; Elmet Orasson; Jaan Raik (VLSI-SoC, 2015)

Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs. - Raimund Ubar; Lembit Jürimägi; Elmet Orasson; Jaan Raik (VLSI-SoC (Selected Papers), 2015)

A tool set for teaching design-for-testability of digital circuits. - Sergei Kostin; Elmet Orasson; Raimund Ubar (EWME, 2016)