Thermal-aware sampling in architectural simulation. - Ehsan K. Ardestani; Elnaz Ebrahimi 001; Gabriel Southern; Jose Renau (ISLPED, 2012)

ESESC: A fast performance, power, and temperature multicore simulator. - Ehsan K. Ardestani; Gabriel Southern; Jason Doung; Elnaz Ebrahimi 001; Jose Renau (Hot Chips Symposium, 2013)

Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation. - Ehsan K. Ardestani; Francisco J. Mesa-Martinez; Gabriel Southern; Elnaz Ebrahimi 001; Jose Renau (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. - Rafael Trapani Possignolo; Elnaz Ebrahimi 001; Haven Blake Skinner; Jose Renau (ICCD, 2016)

SRAM voltage stacking. - Elnaz Ebrahimi 001; Rafael Trapani Possignolo; Jose Renau (ISCAS, 2016)

Timing speculative SRAM. - Elnaz Ebrahimi 001; Matthew R. Guthaus; Jose Renau (ISCAS, 2017)

Level shifter design for voltage stacking. - Elnaz Ebrahimi 001; Rafael Trapani Possignolo; Jose Renau (ISCAS, 2017)

Voltage Stacking and Timing Speculation with an SRAM Focus - Elnaz Ebrahimi 001 (2017)

Automated Pipeline Transformations with Fluid Pipelines. - Rafael Trapani Possignolo; Elnaz Ebrahimi 001; Haven Blake Skinner; Jose Renau (Advanced Logic Synthesis, 2018)

GPU NTC Process Variation Compensation With Voltage Stacking. - Rafael Trapani Possignolo; Elnaz Ebrahimi 001; Ehsan K. Ardestani; Alamelu Sankaranarayanan; José Luis Briz; Jose Renau (IEEE Trans. Very Large Scale Integr. Syst., 2018)