Secure storage using a sealing proxy. - Emanuele Cesena; Gianluca Ramunno; Davide Vernizzi (EUROSEC, 2008)

Towards Trusted Broadcast Encryption. - Emanuele Cesena; Gianluca Ramunno; Davide Vernizzi (ICYCS, 2008)

Pairing with Supersingular Trace Zero Varieties Revisited. - Emanuele Cesena (IACR Cryptol. ePrint Arch., 2008)

Anonymous Services - Enhancing End-user Privacy Exploiting Anonymous Networks. - Giovanni Cabiddu; Emanuele Cesena; Davide Vernizzi (SECRYPT, 2010)

Anonymous Authentication with TLS and DAA. - Emanuele Cesena; Hans Löhr; Gianluca Ramunno; Ahmad-Reza Sadeghi; Davide Vernizzi (TRUST, 2010)

On scalability of remote attestation. - Emanuele Cesena; Gianluca Ramunno; Roberto Sassu; Davide Vernizzi; Antonio Lioy (STC@CCS, 2011)

Typing a Core Binary-Field Arithmetic in a Light Logic. - Emanuele Cesena; Marco Pedicini; Luca Roversi (FOPARA, 2011)

A Unified Ontology for the Virtualization Domain. - Jacopo Silvestro; Daniele Canavese; Emanuele Cesena; Paolo Smiraglia (OTM Conferences (2), 2011)

The Trusted Platform Agent. - Giovanni Cabiddu; Emanuele Cesena; Roberto Sassu; Davide Vernizzi; Gianluca Ramunno; Antonio Lioy (IEEE Softw., 2011)

Can a Light Typing Discipline Be Compatible with an Efficient Implementation of Finite Fields Inversion? - Daniele Canavese; Emanuele Cesena; Rachid Ouchary; Marco Pedicini; Luca Roversi (FOPARA, 2013)

Light combinators for finite fields arithmetic. - Daniele Canavese; Emanuele Cesena; Rachid Ouchary; Marco Pedicini; Luca Roversi (Sci. Comput. Program., 2015)

FPGA Acceleration of Multi-Scalar Multiplication: CycloneMSM. - Kaveh Aasaraai; Don Beaver; Emanuele Cesena; Rahul Maganti; Nicolas Stalder; Javier Varela (IACR Cryptol. ePrint Arch., 2022)

CycloneNTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms. - Kaveh Aasaraai; Emanuele Cesena; Rahul Maganti; Nicolas Stalder; Javier Varela; Kevin Bowers (IACR Cryptol. ePrint Arch., 2022)

Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms. - Kaveh Aasaraai; Emanuele Cesena; Rahul Maganti; Nicolas Stalder; Javier Varela; Kevin Bowers (FPGA, 2023)