A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture. - Yasuro Shobatake; Masahiko Motoyama; Emiko Shobatake; Takashi Kamitake; Shoichi Shimizu; Makoto Noda; Kenji Sakaue (IEEE J. Sel. Areas Commun., 1991)