Synchronous Transfer Architecture (STA). - Gordon Cichon; Pablo Robelly; Hendrik Seidel; Emil Matús; Marcus Bronzel; Gerhard P. Fettweis (SAMOS, 2004)

Generated DSP Cores for Implementation of an OFDM Communication System. - Hendrik Seidel; Emil Matús; Gordon Cichon; Pablo Robelly; Marcus Bronzel; Gerhard P. Fettweis (SAMOS, 2004)

A Compiler-friendly and Low-power DSP architecture. - Emil Matús; Gordon Cichon; Hendrik Seidel; Pablo Robelly; Torsten Limberg; Gerhard P. Fettweis (GI Jahrestagung (1), 2005)

Code Generation for STA Architecture. - Jie Guo 007; Torsten Limberg; Emil Matús; Björn Mennenga; Reimund Klemm; Gerhard P. Fettweis (Euro-Par, 2006)

A High-Throughput Programmable Decoder for LDPC Convolutional Codes. - Marcel Bimberg; Marcos B. S. Tavares; Emil Matús; Gerhard P. Fettweis (ASAP, 2007)

Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes. - Emil Matús; Marcos B. S. Tavares; Marcel Bimberg; Gerhard P. Fettweis (ISCAS, 2007)

Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes. - Marcos B. S. Tavares; Steffen Kunze; Emil Matús; Gerhard P. Fettweis (ASAP, 2008)

A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals. - Torsten Limberg; Markus Winter 002; Marcel Bimberg; Reimund Klemm; Emil Matús; Marcos B. S. Tavares; Gerhard P. Fettweis; Hendrik Ahlendorf; Pablo Robelly (ESSCIRC, 2008)

A dual-core programmable decoder for LDPC convolutional codes. - Marcos B. S. Tavares; Emil Matús; Steffen Kunze; Gerhard P. Fettweis (ISCAS, 2008)

On the performance and numerical stability of soft-decision Reed-Solomon decoding. - Marcel Bimberg; Emil Matús; Gerhard P. Fettweis (EUSIPCO, 2009)

ICT-Emuco. An innovative solution for future smart phones. - Maria Elizabeth Gonzalez; Attila Bilgic; Adam Lackorzynski; Dacian Tudor; Emil Matús; Irv Badr (ICME, 2009)

ASIP Decoder Architecture for Convolutional and LDPC Codes. - Steffen Kunze; Emil Matús; Gerhard P. Fettweis (ISCAS, 2009)

Vectorization of the Sphere Detection Algorithm. - Björn Mennenga; Emil Matús; Gerhard P. Fettweis (ISCAS, 2009)

On the Structured Parallelism of Decoders for LDPC Convolutional Codes - an Algebraic Description. - Marcos B. S. Tavares; Emil Matús; Gerhard P. Fettweis (ISCAS, 2009)

Combining LDPC, turbo and Viterbi decoders: Benefits and costs. - Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Tomoyoshi Kobori (SiPS, 2011)

A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. - Markus Winter 002; Steffen Kunze; Esther P. Adeva; Björn Mennenga; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Sebastian Höppner; Stefan Scholze; René Schüffny; Tomoyoshi Kobori (ISSCC, 2012)

Two-stage detector for SC-FDMA transmission over MIMO ISI channels. - Marcel Jar; Emil Matús; Esther P. Adeva; Eckhard Ohlmer; Gerhard P. Fettweis (ISWCS, 2012)

Towards elastic SDR architectures using dynamic task management. - Oliver Arnold; Emil Matús; Benedikt Noethen; Friedrich Pauls; Gerhard P. Fettweis (GlobalSIP, 2013)

EUROSERVER: Energy Efficient Node for European Micro-Servers. - Yves Durand; Paul M. Carpenter; Stefano Adami; Angelos Bilas; Denis Dutoit; Alexis Farcy; Georgi Gaydadjiev; John Goodacre; Manolis Katevenis; Manolis Marazakis; Emil Matús; Iakovos Mavroidis; et al. (DSD, 2014)

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. - Benedikt Noethen; Oliver Arnold; Esther P. Adeva; Tobias Seifert; Erik Fischer; Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Stephan Hartmann 002; Sebastian Höppner; et al. (ISSCC, 2014)

Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs. - Oliver Arnold; Emil Matús; Benedikt Noethen; Markus Winter 002; Torsten Limberg; Gerhard P. Fettweis (ACM Trans. Embed. Comput. Syst., 2014)

Centralized parallel multi-path multi-slot allocation approach for TDM NoCs. - Yong Chen 014; Emil Matús; Gerhard P. Fettweis (CCECE, 2016)

An MPSoC for energy-efficient database query processing. - Sebastian Haas; Oliver Arnold; Benedikt Nöthen; Stefan Scholze; Georg Ellguth; Andreas Dixius; Sebastian Höppner; Stefan Schiefer; Stephan Hartmann 002; Stephan Henker; Thomas Hocker; Jörg Schreiter; et al. (DAC, 2016)

EUROSERVER: Share-anything scale-out micro-server design. - Manolis Marazakis; John Goodacre; Didier Fuin; Paul M. Carpenter; John Thomson; Emil Matús; Antimo Bruno; Per Stenström; Jérôme Martin; Yves Durand; Isabelle Dor (DATE, 2016)

Trellis-search based Dynamic Multi-Path Connection Allocation for TDM-NoCs. - Yong Chen 014; Emil Matús; Gerhard P. Fettweis (ACM Great Lakes Symposium on VLSI, 2016)

A database accelerator for energy-efficient query processing and optimization. - Sebastian Haas; Oliver Arnold; Stefan Scholze; Sebastian Höppner; Georg Ellguth; Andreas Dixius; Annett Ungethüm; Eric Mier; Benedikt Noethen; Emil Matús; Stefan Schiefer; Love Cederstroem; et al. (NORCAS, 2016)

Scalable 5G MPSoC architecture. - Gerhard P. Fettweis; Emil Matús (ACSSC, 2017)

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. - Sebastian Haas; Tobias Seifert; Benedikt Nöthen; Stefan Scholze; Sebastian Höppner; Andreas Dixius; Esther Pérez Adeva; Thomas R. Augustin; Friedrich Pauls; Sadia Moriam; Mattis Hasler; Erik Fischer; et al. (DAC, 2017)

Combined Centralized and Distributed Connection Allocation in Large TDM Circuit Switching NoCs. - Yong Chen 014; Emil Matús; Gerhard P. Fettweis (ACM Great Lakes Symposium on VLSI, 2017)

Combined packet and TDM circuit switching NoCs with novel connection configuration mechanism. - Yong Chen 014; Emil Matús; Gerhard P. Fettweis (ISCAS, 2017)

Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection Allocator. - Yong Chen 014; Emil Matús; Gerhard P. Fettweis (ISVLSI, 2017)

Register-Exchange Based Connection Allocator for Circuit Switching NoCs. - Yong Chen 014; Emil Matús; Gerhard P. Fettweis (PDP, 2017)

DF4CRAN: Dataflow Framework for Cloud-RAN Signal Processing. - Nairuhi Grigoryan; Emil Matús; Gerhard P. Fettweis (5G World Forum, 2019)

A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel. - Gerhard P. Fettweis; Mattis Hasler; Robert Wittig; Emil Matús; Stefan A. Damjancevic; Sebastian Haas; Friedrich Pauls; Seungseok Nam; Nairuhi Grigoryan (ACSSC, 2019)

Statistical Access Interval Prediction for Tightly Coupled Memory Systems. - Robert Wittig; Mattis Hasler; Emil Matús; Gerhard P. Fettweis (COOL CHIPS, 2019)

Queue Based Memory Management Unit for Heterogeneous MPSoCs. - Robert Wittig; Mattis Hasler; Emil Matús; Gerhard P. Fettweis (DATE, 2019)

General Multicarrier Modulation Hardware Accelerator for the Internet of Things. - Robert Wittig; Stefan A. Damjancevic; Emil Matús; Gerhard P. Fettweis (GLOBECOM, 2019)

A Hybrid Execution Approach to Improve the Performance of Dataflow Applications. - Mattis Hasler; Robert Wittig; Emil Matús; Gerhard P. Fettweis (ISOCC, 2019)

Access Interval Prediction for Tightly Coupled Memory Systems. - Robert Wittig; Friedrich Pauls; Emil Matús; Gerhard P. Fettweis (SAMOS, 2019)

Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs. - Seungseok Nam; Emil Matús; Gerhard P. Fettweis (SoCC, 2019)

5G-and-Beyond Scalable Machines. - Gerhard P. Fettweis; Emil Matús; Robert Wittig; Mattis Hasler; Stefan A. Damjancevic; Seungseok Nam; Sebastian Haas (VLSI-SoC, 2019)

Probabilistic Models for Off-Line Arbiters in Embedded Systems. - Robert Wittig; Mattis Hasler; Emil Matús; Gerhard P. Fettweis (VLSI-SoC, 2019)

Towards GFDM for Handsets - Efficient and Scalable Implementation on a Vector DSP. - Stefan A. Damjancevic; Emil Matús; Dmitry Utyansky; Pieter van der Wolf; Gerhard P. Fettweis (VTC Fall, 2019)

Scalable 5G Signal Processing on Multiprocessor System: A Clustering Approach. - Nairuhi Grigoryan; Emil Matús; Gerhard P. Fettweis (5G World Forum, 2020)

Balancing Dynamic Scheduling Overhead to Maximize SDF Performance. - Mattis Hasler; Robert Wittig; Emil Matús; Gerhard P. Fettweis (6G SUMMIT, 2020)

Low Complexity Convolutional Neural Networks for Wireless Receiver Chain Optimization. - Mohammed Radi; Emil Matús; Gerhard P. Fettweis (IEEE ANTS, 2020)

An ASIP Approach to Path Allocation in TDM NoCs using Adaptive Search Region. - Seungseok Nam; Emil Matús; Gerhard P. Fettweis (ACM Great Lakes Symposium on VLSI, 2020)

Modem Design in the Era of 5G and Beyond: The Need for a Formal Approach. - Robert Wittig; Andrés Goens; Christian Menard; Emil Matús; Gerhard P. Fettweis; Jerónimo Castrillón (ICT, 2020)

Path-Spreading Search Algorithm and ASIP Approach for Connection Allocation in TDM-NoCs. - Seungseok Nam; Emil Matús; Sadia Moriam; Gerhard P. Fettweis (ISVLSI, 2020)

Channel Profile Independent Usage of Convolutional Neural Networks for Receiver Chain Optimization. - Mohammed Radi; Emil Matús; Gerhard P. Fettweis (LATINCOM, 2020)

Blind Packet-Based Receiver Chain Optimization Using Machine Learning. - Mohammed Radi; Emil Matús; Gerhard P. Fettweis (WCNC, 2020)

Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion. - Mattis Hasler; Robert Wittig; Emil Matús; Gerhard P. Fettweis (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

High Performance Dynamic Resource Allocation for Guaranteed Service in Network-on-Chips. - Yong Chen 014; Emil Matús; Sadia Moriam; Gerhard P. Fettweis (IEEE Trans. Emerg. Top. Comput., 2020)

Minimized Region of Path-search Algorithm for ASIP-based Connection Allocator in NoCs. - Seungseok Nam; Emil Matús; Gerhard P. Fettweis (ISVLSI, 2021)

Flexible Channel Estimation for 3GPP 5G IoT on a Vector Digital Signal Processor. - Stefan A. Damjancevic; Samuel Ajay Dasgupta; Emil Matús; Dmitry Utyanksy; Pieter van der Wolf; Gerhard P. Fettweis (SiPS, 2021)

Digital Predistortion with Compressed Observations for Cloud-Based Learning. - Arne Fischer-Bühner; Emil Matús; Manil Dev Gomony; Lauri Anttila; Gerhard P. Fettweis; Mikko Valkama (SiPS, 2021)

Energy efficiency optimization of radiofrequency power amplifiers for massive MIMO: a data based approach. - Luis Godoy; Emil Matús; Gerhard P. Fettweis (SPAWC, 2021)

Channel Estimation for Advanced 5G/6G Use Cases on a Vector Digital Signal Processor. - Stefan A. Damjancevic; Emil Matús; Dmitry Utyansky; Pieter van der Wolf; Gerhard P. Fettweis (IEEE Open J. Circuits Syst., 2021)

Efficient Synchronization for NR-REDCAP Implemented on a Vector DSP. - Sheikh Faizan Qureshi; Stefan A. Damjancevic; Emil Matús; Dmitry Utyansky; Pieter van der Wolf; Gerhard P. Fettweis (ASAP, 2022)

Communications Signal Processing Using RISC-V Vector Extension. - Viktor Razilov; Emil Matús; Gerhard P. Fettweis (IWCMC, 2022)

Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory Systems. - Viktor Razilov; Robert Wittig; Emil Matús; Gerhard P. Fettweis (SAMOS, 2022)

Accurate Estimation of Service Rates in Interleaved Scratchpad Memory Systems. - Robert Wittig; Philipp Schulz; Emil Matús; Gerhard P. Fettweis (ACM Trans. Embed. Comput. Syst., 2022)

Optimal SDNR Digital Predistortion via Direct Inversion. - Luis Godoy; Andrés Villamil; Emil Matús; Gerhard P. Fettweis (ACSSC, 2023)

Dual Vector Load for Improved Pipelining in Vector Processors. - Viktor Razilov; Juncen Zhong; Emil Matús; Gerhard P. Fettweis (COOL CHIPS, 2023)

The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective. - Fabian Kempf; Julian Höfer; Tanja Harbaum; Jürgen Becker 001; Nael Fasfous; Alexander Frickenstein; Hans-Jörg Vögel; Simon Friedrich; Robert Wittig; Emil Matús; Gerhard P. Fettweis; Matthias Lüders; et al. (DATE, 2023)

Access Interval Prediction with Neural Networks for Tightly Coupled Memory Systems. - Simon Friedrich; Chia-Ying Lin; Viktor Razilov; Robert Wittig; Emil Matús; Gerhard P. Fettweis (DSD, 2023)

Energy Efficiency Analysis of RF Power Amplifier Digital Predistortion in Full-Digital MIMO Transmitters. - Luis Godoy; Emil Matús; Gerhard P. Fettweis (ICC Workshops, 2023)

Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands. - Simon Friedrich; Shambhavi Balamuthu Sampath; Robert Wittig; Manoj Rohit Vemparala; Nael Fasfous; Emil Matús; Walter Stechele; Gerhard P. Fettweis (ISQED, 2023)

Energy-Efficient Virtual Optical Network Embedding Over Mixed-Grid Optical Networks. - Joy Halder; Emil Matús; Gerhard P. Fettweis (NFV-SDN, 2023)

On-Chip Memory Access Reduction for Energy-Efficient Dilated Convolution Processing. - Simon Friedrich; Thomas Nalapat; Robert Wittig; Emil Matús; Gerhard P. Fettweis (SAMOS, 2023)

A 22 nm 10 TOPS Mixed-Precision Neural Network SoC for Image Processing with Energy-Efficient Dilated Convolution Support. - Simon Friedrich; Robert Wittig; Emil Matús; Darius Grantz; Martin Zeller; Jens Benndorf; Gerhard P. Fettweis (COOL CHIPS, 2024)

On the Concurrent Multipath Entanglement Distribution in Quantum Networks. - Joy Halder; Emil Matús; Gerhard P. Fettweis (GLOBECOM, 2024)

ZuSE-KI-Mobil AI Chip Design Platform: An Overview. - Shaown Mojumder; Simon Friedrich; Emil Matús; Gerhard P. Fettweis; Matthias Lüders; Martin Friedrich; Oliver Renke; Holger Blume; Julian Höfer; Patrick Schmidt; Jürgen Becker 001; Darius Grantz; et al. (NorCAS, 2024)

Implementation of the Tagged Geometric History Length Access Interval Predictor. - Viktor Razilov; Emil Matús; Gerhard P. Fettweis (NorCAS, 2024)

Box Decoding: A Low-Complexity Algorithm for MIMO Detection. - Sheikh Faizan Qureshi; Stefan A. Damjancevic; Emil Matús; Dmitry Utyansky; Pieter van der Wolf; Gerhard P. Fettweis (SiPS, 2024)

Access Interval Prediction by Partial Matching for Tightly Coupled Memory Systems. - Viktor Razilov; Robert Wittig; Emil Matús; Gerhard P. Fettweis (Int. J. Parallel Program., 2024)

Efficient Handover Mode Synchronization for NR-REDCAP on a Vector DSP. - Sheikh Faizan Qureshi; Stefan A. Damjancevic; Emil Matús; Pieter van der Wolf; Dmitry Utyansky; Gerhard P. Fettweis (J. Signal Process. Syst., 2024)

Conflict Management in Vector Register Files. - Viktor Razilov; Ipek Geçin; Emil Matús; Gerhard P. Fettweis (ACM Trans. Archit. Code Optim., 2025)