Timing optimization by an improved redundancy addition and removal technique. - Luis Entrena; Emilio Olías; Javier Uceda; José Alberto Espejo (EURO-DAC, 1996)

Logic Restructuring for MUX-Based FPGAs. - José Alberto Espejo; Luis Entrena; Enrique San Millán; Emilio Olías (EUROMICRO, 1999)

Functional extension of structural logic optimization techniques. - José Alberto Espejo; Luis Entrena; Enrique San Millán; Emilio Olías (ASP-DAC, 2001)

Generalized reasoning scheme for redundancy addition and removal logic optimization. - José Alberto Espejo; Luis Entrena; Enrique San Millán; Emilio Olías (DATE, 2001)

Automatic Insertion of Fault-Tolerant Structures at the RT Level. - Luis Entrena; Celia López; Emilio Olías (IOLTW, 2001)

Logic Optimization of Unidirectional Circuits with Structural Methods. - Luis Entrena; Celia López; Emilio Olías; Enrique San Millán; José Alberto Espejo (IOLTW, 2001)

A procedure to model the frequency response. - J. Pleite; Emilio Olías; Andrés Barrado; Antonio Lázaro 002; J. Váquez (SAC, 2002)

New Power Factor Correction AC-DC Converter With Reduced Storage Capacitor Voltage. - Antonio Lázaro 002; Andrés Barrado; Marina Sanz; Vicente Salas; Emilio Olías (IEEE Trans. Ind. Electron., 2007)

Dual active bridge with triple phase shift, soft switching and minimum RMS current for the whole operating range. - Carlos Calderón; Andrés Barrado; Alberto Rodriguez 001; Antonio Lázaro 002; Marina Sanz; Emilio Olías (IECON, 2017)

Numerical and Experimental Evaluation and Heat Transfer Characteristics of a Soft Magnetic Transformer Built from Laminated Steel Plates. - Eduardo Cano-Pleite; Andrés Barrado; Néstor Garcia-Hernando; Emilio Olías; Antonio Soria-Verdugo (Sensors, 2021)