A Linear Systolic Array for LU Decomposition. - Emmanuel Casseau; Dominique Degrugillier (VLSI Design, 1994)

High Rate Soft Output Viterbi Decoder. - Eric Lüthi; Emmanuel Casseau (ED&TC, 1996)

Architecture of a high-rate VLSI Viterbi decoder. - Emmanuel Casseau; Eric Lüthi (ICECS, 1996)

Architectural Synthesis with Interconnection Cost Control. - Christophe Jégo; Emmanuel Casseau; Eric Martin 001 (VLSI, 1999)

Architectural synthesis of digital signal processing applications dedicated to submicron technologies. - Emmanuel Casseau; Christophe Jégo; Eric Martin 001 (ICECS, 2001)

SoC design using behavioral level virtual components. - Emmanuel Casseau (ICECS, 2002)

Reed-Solomon behavioral virtual component for communication systems. - Emmanuel Casseau; Bertrand Le Gal; Christophe Jégo; Nathalie Le Heno; Eric Martin 001 (ISCAS (4), 2004)

Synthèse architecturale d'applications temps réel pour technologies submicroniques. - Emmanuel Casseau; Christophe Jégo; Eric Martin 001 (Tech. Sci. Informatiques, 2004)

Hardware Virtual Components Compliant with Communication System Standards. - Nabil Abdelli; Pierre Bomel; Emmanuel Casseau; Anne-Marie Fouilliart; Christophe Jégo; Philippe Kajfasz; Bertrand Le Gal; Nathalie Le Heno (DSD, 2005)

C-based rapid prototyping for digital signal processing. - Emmanuel Casseau; Bertrand Le Gal; Pierre Bomel; Christophe Jégo; Sylvain Huet; Eric Martin 001 (EUSIPCO, 2005)

Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. - Bertrand Le Gal; Emmanuel Casseau; Eric Martin 001 (EUSIPCO, 2005)

Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. - Bertrand Le Gal; Emmanuel Casseau; Sylvain Huet; Eric Martin 001 (ISVLSI, 2005)

Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. - Sylvain Huet; Emmanuel Casseau; Olivier Pasquier (IEEE International Workshop on Rapid System Prototyping, 2005)

A Computation Core for Communication Refinement of Digital Signal Processing Algorithms. - Sylvain Huet; Emmanuel Casseau; Olivier Pasquier (DSD, 2006)

Hardware Communication Refinement in Digital Signal Processing. - Sylvain Huet; Emmanuel Casseau; Olivier Pasquier; Sébastien Le Nours (FDL, 2006)

IP Generation Targeting Multiple Bit-Width Standards. - Bertrand Le Gal; Emmanuel Casseau (ICECS, 2006)

Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. - Caaliph Andriamisaina; Bertrand Le Gal; Emmanuel Casseau (SiPS, 2006)

Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems. - Bertrand Le Gal; Caaliph Andriamisaina; Emmanuel Casseau (SoCC, 2006)

Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. - Guillaume Savaton; Emmanuel Casseau; Eric Martin 001 (Signal Process., 2006)

A formal method for hardware IP design and integration under I/O and timing constraints. - Philippe Coussy; Emmanuel Casseau; Pierre Bomel; Adel Baganne; Eric Martin 001 (ACM Trans. Embed. Comput. Syst., 2006)

G729 Voice Decoder Design. - Fatma Sayadi; Emmanuel Casseau; Mohamed Atri; Mehrez Marzougui; Rached Tourki; Eric Martin 001 (J. VLSI Signal Process., 2006)

Synthesis of Multimode digital signal processing systems. - Caaliph Andriamisaina; Emmanuel Casseau; Philippe Coussy (AHS, 2007)

Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications. - Sylvain Huet; Sébastien Le Nours; Olivier Pasquier; Emmanuel Casseau (FDL, 2007)

A design flow dedicated to multi-mode architectures for DSP applications. - Cyrille Chavet; Caaliph Andriamisaina; Philippe Coussy; Emmanuel Casseau; Emmanuel Juin; Pascal Urard; Eric Martin 001 (ICCAD, 2007)

HLS design flow for the synthesis of multimode systems under multiple constraints. - Bertrand Le Gal; Lilian Bossuet; Shafqat Khan; Emmanuel Casseau (ICECS, 2007)

Constrained algorithmic IP design for system-on-chip. - Philippe Coussy; Emmanuel Casseau; Pierre Bomel; Adel Baganne; Eric Martin 001 (Integr., 2007)

Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau. - Bertrand Le Gal; Emmanuel Casseau; Caaliph Andriamisaina (Tech. Sci. Informatiques, 2008)

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. - Bertrand Le Gal; Emmanuel Casseau; Sylvain Huet (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Reconfigurable Operator Based Multimedia Embedded Processor. - Daniel Ménard; Emmanuel Casseau; Shafqat Khan; Olivier Sentieys; Stéphane Chevobbe; Stéphane Guyetant; Raphaël David (ARC, 2009)

Reconfigurable SWP Operator for Multimedia Processing. - Shafqat Khan; Emmanuel Casseau; Daniel Ménard (ASAP, 2009)

Automated multimode system design for high performance DSP applications. - Bertrand Le Gal; Emmanuel Casseau (EUSIPCO, 2009)

High-level synthesis for the design of FPGA-based signal processing systems. - Emmanuel Casseau; Bertrand Le Gal (ICSAMOS, 2009)

A case study of the stochastic modeling approach for range estimation. - Andrei Banciu; Emmanuel Casseau; Daniel Ménard; Thierry Michel (DASIP, 2010)

A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design. - Cecile Beaumin; Olivier Sentieys; Emmanuel Casseau; Arnaud Carer (DASIP, 2010)

Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture. - Erwan Raffin; Christophe Wolinski; François Charot; Krzysztof Kuchcinski; Stéphane Guyetant; Stéphane Chevobbe; Emmanuel Casseau (DASIP, 2010)

High-Level Synthesis for Designing Multimode Architectures. - Caaliph Andriamisaina; Philippe Coussy; Emmanuel Casseau; Cyrille Chavet (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Efficient custom instruction enumeration for extensible processors. - Chenglong Xiao; Emmanuel Casseau (ASAP, 2011)

Efficient maximal convex custom instruction enumeration for extensible processors. - Chenglong Xiao; Emmanuel Casseau (DASIP, 2011)

An efficient algorithm for custom instruction enumeration. - Chenglong Xiao; Emmanuel Casseau (ACM Great Lakes Symposium on VLSI, 2011)

Exploiting reconfigurable SWP operators for multimedia applications. - Daniel Ménard; Hai-Nam Nguyen; François Charot; Stéphane Guyetant; Jérémie Guillot; Erwan Raffin; Emmanuel Casseau (ICASSP, 2011)

Stochastic modeling for floating-point to fixed-point conversion. - Andrei Banciu; Emmanuel Casseau; Daniel Ménard; Thierry Michel (SiPS, 2011)

Efficient multicore scheduling of dataflow process networks. - Hervé Yviquel; Emmanuel Casseau; Matthieu Wipliez; Mickaël Raulet (SiPS, 2011)

Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. - Bertrand Le Gal; Emmanuel Casseau (EURASIP J. Adv. Signal Process., 2011)

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. - Bertrand Le Gal; Emmanuel Casseau (J. Signal Process. Syst., 2011)

Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture. - Erwan Raffin; Christophe Wolinski; François Charot; Emmanuel Casseau; Antoine Floch; Krzysztof Kuchcinski; Stéphane Chevobbe; Stéphane Guyetant (Int. J. Embed. Real Time Commun. Syst., 2012)

Design of multi-mode application-specific cores based on high-level synthesis. - Emmanuel Casseau; Bertrand Le Gal (Integr., 2012)

Exact custom instruction enumeration for extensible processors. - Chenglong Xiao; Emmanuel Casseau (Integr., 2012)

Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms. - Hervé Yviquel; Emmanuel Casseau; Mickaël Raulet; Pekka Jääskeläinen; Jarmo Takala (ISPA, 2013)

Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs. - Hervé Yviquel; Jani Boutellier; Mickaël Raulet; Emmanuel Casseau (Signal Process. Image Commun., 2013)

Orcc's compa-backend demonstration. - Yaset Oliva; Emmanuel Casseau; Kevin J. M. Martin; Pierre Bomel; Jean-Philippe Diguet; Hervé Yviquel; Mickaël Raulet; Erwan Raffin; Laurent Morin (DASIP, 2014)

Efficient software synthesis of dynamic dataflow programs. - Hervé Yviquel; Alexandre Sanchez; Pekka Jääskeläinen; Jarmo Takala; Mickaël Raulet; Emmanuel Casseau (ICASSP, 2014)

Improving high-level synthesis effectiveness through custom operator identification. - Chenglong Xiao; Emmanuel Casseau (ISCAS, 2014)

Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture. - Quang-Hoa Le; Emmanuel Casseau; Antoine Courtay (ReConFig, 2014)

Automatic custom instruction identification for application-specific instruction set processors. - Chenglong Xiao; Emmanuel Casseau; Shanshan Wang; Wanjun Liu (Microprocess. Microsystems, 2014)

Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms. - Kevin J. M. Martin; Yvan Eustache; Jean-Philippe Diguet; Thanh Dinh Ngo; Emmanuel Casseau; Yaset Oliva (DASIP, 2015)

Selecting most profitable instruction-set extensions using ant colony heuristic. - Shanshan Wang; Chenglong Xiao; Wanjun Liu; Emmanuel Casseau; Xiao Yang (DASIP, 2015)

Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m). - Jérémy Métairie; Arnaud Tisserand; Emmanuel Casseau (ISVLSI, 2015)

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs. - Hervé Yviquel; Alexandre Sanchez; Pekka Jääskeläinen; Jarmo Takala; Mickaël Raulet; Emmanuel Casseau (J. Signal Process. Syst., 2015)

On the FPGA-Based Implementation of a Flexible Waveform from a High-Level Description: Application to LTE FFT Case Study. - Mai-Thanh Tran; Matthieu Gautier; Emmanuel Casseau (CrownCom, 2016)

Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standard. - Mai-Thanh Tran; Emmanuel Casseau; Matthieu Gautier (DASIP, 2016)

A comparison of heuristic algorithms for custom instruction selection. - Shanshan Wang; Chenglong Xiao; Wanjun Liu; Emmanuel Casseau (Microprocess. Microsystems, 2016)

An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy. - Imran Wali; Emmanuel Casseau; Arnaud Tisserand (DASIP, 2017)

Parallel custom instruction identification for extensible processors. - Chenglong Xiao; Shanshan Wang; Wanjun Liu; Emmanuel Casseau (J. Syst. Archit., 2017)

Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems. - Petr Dobiás; Emmanuel Casseau; Oliver Sinnen (DASIP, 2018)

Restricted Scheduling Windows for Dynamic Fault-Tolerant Primary/Backup Approach-Based Scheduling on Embedded Systems. - Petr Dobiás; Emmanuel Casseau; Oliver Sinnen (SCOPES, 2018)

Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors. - Rafail Psiakis; Angeliki Kritikakou; Olivier Sentieys; Emmanuel Casseau (DASIP, 2019)

Evaluation of Fault Tolerant Online Scheduling Algorithms for CubeSats. - Petr Dobiás; Emmanuel Casseau; Oliver Sinnen (DSD, 2020)

Fault-Tolerant Online Scheduling Algorithms for CubeSats. - Petr Dobiás; Emmanuel Casseau; Oliver Sinnen (PARMA-DITAM@HiPEAC, 2020)

Energy-Aware Partial-Duplication Task Mapping Under Real-Time and Reliability Constraints. - Minyu Cui; Lei Mo; Angeliki Kritikakou; Emmanuel Casseau (SAMOS, 2020)

MASCARA (ModulAr Semantic CAching fRAmework) towards FPGA Acceleration for IoT Security Monitoring. - Van Long Nguyen Huu; Julien Lallet; Emmanuel Casseau; Laurent d'Orazio (Open J. Internet Things, 2020)

Fault-Tolerant Mapping of Real-Time Parallel Applications under multiple DVFS schemes. - Minyu Cui; Angeliki Kritikakou; Lei Mo; Emmanuel Casseau (RTAS, 2021)

MASCARA-FPGA cooperation model: Query Trimming through accelerators. - Van Long Nguyen Huu; Laurent d'Orazio; Emmanuel Casseau; Julien Lallet (SSDBM, 2021)

Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum. - Emmanuel Casseau; Petr Dobiás; Oliver Sinnen; Gennaro Severino Rodrigues; Fernanda Lima Kastensmidt; Alessandro Savino; Stefano Di Carlo; Maurizio Rebaudengo; Alberto Bosio (VTS, 2021)

An algorithm with improved delay for enumerating connected induced subgraphs of a large cardinality. - Shanshan Wang; Chenglong Xiao; Emmanuel Casseau (CoRR, 2021)

An Optimal Algorithm for Enumerating Connected Convex Subgraphs in Acyclic Digraphs. - Chenglong Xiao; Shanshan Wang; Wanjun Liu; Xinlin Wang; Emmanuel Casseau (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Improving the CubeSat reliability thanks to a multiprocessor system using fault tolerant online scheduling. - Petr Dobiás; Emmanuel Casseau; Oliver Sinnen (Microprocess. Microsystems, 2021)

Cache management in MASCARA-FPGA: from coalescing heuristic to replacement policy. - Van Long Nguyen Huu; Laurent d'Orazio; Emmanuel Casseau; Julien Lallet (DaMoN, 2022)

Energy-Efficient Partial-Duplication Task Mapping Under Multiple DVFS Schemes. - Minyu Cui; Angeliki Kritikakou; Lei Mo; Emmanuel Casseau (Int. J. Parallel Program., 2022)

Surround the Nonlinearity: Inserting Foldable Convolutional Autoencoders to Reduce Activation Footprint. - Baptiste Rossigneux; Inna Kucher; Vincent Lorrain; Emmanuel Casseau (ICCV (Workshops), 2023)

Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications. - Minyu Cui; Angeliki Kritikakou; Lei Mo; Emmanuel Casseau (J. Syst. Archit., 2023)

Online fault tolerant energy-aware algorithm for CubeSats. - Petr Dobiás; Emmanuel Casseau; Oliver Sinnen (Sustain. Comput. Informatics Syst., 2023)

Importance Resides in Activations: Fast Input-Based Nonlinearity Pruning. - Baptiste Rossigneux; Vincent Lorrain; Inna Kucher; Emmanuel Casseau (ICONIP (9), 2024)

Mitigation of Hardware Trojan in NoC using Delta-Based Compression. - Hamza Amara; Cédric Killian; Daniel Chillet; Emmanuel Casseau (SOCC, 2024)

Algorithms with improved delay for enumerating connected induced subgraphs of a large cardinality. - Shanshan Wang; Chenglong Xiao; Emmanuel Casseau (Inf. Process. Lett., 2024)

Intelligent4DSE: Optimizing High-Level Synthesis Design Space Exploration with Graph Neural Networks and Large Language Models. - Lei Xu; Shanshan Wang; Emmanuel Casseau; Chenglong Xiao (CoRR, 2025)