A Fast Interrupt Handling Scheme for VLIW Processors. - Emre Özer 001; Sumedh W. Sathaye; Kishore N. Menezes; Sanjeev Banerjia; Matthew D. Jennings; Thomas M. Conte (IEEE PACT, 1998)

Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. - Emre Özer 001; Sanjeev Banerjia; Thomas M. Conte (MICRO, 1998)

Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. - Emre Özer 001; Thomas M. Conte; Saurabh Sharma (HiPC, 2001)

Stochastic Bit-Width Approximation Using Extreme Value Theory for Customizable Processors. - Emre Özer 001; Andy Nisbet; David Gregg (CC, 2004)

Automatic Customization of Embedded Applications for Enhanced Performance and Reduced Power Using Optimizing Compiler Techniques. - Emre Özer 001; Andy Nisbet; David Gregg (Euro-Par, 2004)

Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs. - Emre Özer 001; Andy Nisbet; David Gregg (FCCM, 2004)

FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic. - Owen Callanan; Andy Nisbet; Emre Özer 001; James Sexton; David Gregg (IPDPS, 2005)

Multiple-Valued Caches for Power-Efficient Embedded Systems. - Emre Özer 001; Resit Sendag; David Gregg (ISMVL, 2005)

Estimating data bus size for custom processors in embedded systems. - Emre Özer 001; Andy Nisbet; David Gregg; Owen Callanan (Des. Autom. Embed. Syst., 2005)

High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. - Emre Özer 001; Thomas M. Conte (IEEE Trans. Parallel Distributed Syst., 2005)

Efficient System-on-Chip Energy Management with a Segmented Bloom Filter. - Mrinmoy Ghosh; Emre Özer 001; Stuart Biles; Hsien-Hsin S. Lee (ARCS, 2006)

Reducing energy of virtual cache synonym lookup using bloom filters. - Dong Hyuk Woo; Mrinmoy Ghosh; Emre Özer 001; Stuart Biles; Hsien-Hsin S. Lee (CASES, 2006)

Low-Cost Microarchitectural Techniques for Enhancing the Prediction of Return Addresses on High-Performance Trace Cache Processors. - Yunhe Shi; Emre Özer 001; David Gregg (ISCIS, 2006)

Analyzing Effects of Trace Cache Configurations on the Prediction of Indirect Branches. - Yunhe Shi; Emre Özer 001; David Gregg (J. Instr. Level Parallelism, 2006)

Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor. - Emre Özer 001; Stuart Biles (Asia-Pacific Computer Systems Architecture Conference, 2007)

Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor. - Emre Özer 001; Alastair Reid 001; Stuart Biles (SBAC-PAD, 2007)

Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor. - Emre Özer 001; Ronald G. Dreslinski; Trevor N. Mudge; Stuart Biles; Krisztián Flautner (SAMOS, 2008)

A stochastic bitwidth estimation technique for compact and low-power custom processors. - Emre Özer 001; Andy Nisbet; David Gregg (ACM Trans. Embed. Comput. Syst., 2008)

Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches. - Mrinmoy Ghosh; Emre Özer 001; Simon Ford; Stuart Biles; Hsien-Hsin S. Lee (ISLPED, 2009)

Radiation hardening by design: A novel gate level approach. - Massoud Mokhtarpour Ghahroodi; Mark Zwolinski; Emre Özer 001 (AHS, 2011)

Eliminating energy of same-content-cell-columns of on-chip SRAM arrays. - Bushra Ahsan; Lorena Ndreu; Isidoros Sideris; Yiannakis Sazeides; Sachin Idgunji; Emre Özer 001 (ISLPED, 2011)

Thermal characterization of cloud workloads on a power-efficient server-on-chip. - Dragomir Milojevic; Sachin Idgunji; Djordje Jevdjic; Emre Ozer 001; Pejman Lotfi-Kamran; Andreas Panteli; Andreas Prodromou; Chrysostomos Nicopoulos; Damien Hardy; Babak Falsafi; Yiannakis Sazeides (ICCD, 2012)

Scale-out processors. - Pejman Lotfi-Kamran; Boris Grot; Michael Ferdman; Stavros Volos; Yusuf Onur Koçberber; Javier Picorel; Almutaz Adileh; Djordje Jevdjic; Sachin Idgunji; Emre Ozer 001; Babak Falsafi (ISCA, 2012)

Memory array protection: check on read or check on write? - Panagiota Nikolaou; Yiannakis Sazeides; Lorena Ndreu; Emre Özer 001; Sachin Idgunji (DATE, 2013)

An analytical framework for estimating TCO and exploring data center design space. - Damien Hardy; Marios Kleanthous; Isidoros Sideris; Ali G. Saidi; Emre Ozer 001; Yiannakis Sazeides (ISPASS, 2013)

Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes. - Yiannakis Sazeides; Emre Özer 001; Danny Kershaw; Panagiota Nikolaou; Marios Kleanthous; Jaume Abella 001 (MICRO, 2013)

Towards a generic and adaptive System-on-Chip controller for space exploration instrumentation. - Xabier Iturbe; Didier Keymeulen; Patrick Yiu; Dan Berisford; Kevin P. Hand; Robert Carlson; Emre Ozer 001 (AHS, 2015)

A Highly-Efficient, Adaptive and Fault-Tolerant SoC Implementation of a Fourier Transform Spectrometer Data Processing. - Xabier Iturbe; Didier Keymeulen; Patrick Yiu; Dan Berisford; Kevin P. Hand; Robert Carlson; Emre Ozer 001 (FCCM, 2015)

Designing a SoC to control the next-generation space exploration flight science instruments. - Xabier Iturbe; Didier Keymeulen; Emre Ozer 001; Patrick Yiu; Daniel Berisford; Kevin P. Hand; Robert Carlson (SoCC, 2015)

An integrated SoC for science data processing in next-generation space flight instruments avionics. - Xabier Iturbe; Didier Keymeulen; Emre Ozer 001; Patrick Yiu; Daniel Berisford; Kevin P. Hand; Robert Carlson (VLSI-SoC, 2015)

On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploration. - Xabier Iturbe; Didier Keymeulen; Patrick Yiu; Daniel Berisford; Robert Carlson; Kevin P. Hand; Emre Ozer 001 (VLSI-SoC (Selected Papers), 2015)

Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU. - Xabier Iturbe; Balaji Venu; Emre Ozer 001 (DFT, 2016)

A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications. - Xabier Iturbe; Balaji Venu; Emre Ozer 001; Shidhartha Das (DSN Workshops, 2016)

Predicting room occupancy with a single passive infrared (PIR) sensor through behavior extraction. - Yordan P. Raykov; Emre Ozer 001; Ganesh Dasika; Alexis Boukouvalas; Max A. Little (UbiComp, 2016)

Toward Multi-Layer Holistic Evaluation of System Designs. - Marios Kleanthous; Yiannakis Sazeides; Emre Özer 001; Chrysostomos Nicopoulos; Panagiota Nikolaou; Zacharias Hadjilambrou (IEEE Comput. Archit. Lett., 2016)

Visual IoT: Architectural Challenges and Opportunities; Toward a Self-Learning and Energy-Neutral IoT. - Ravi R. Iyer 001; Emre Ozer 001 (IEEE Micro, 2016)

A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress. - Xabier Iturbe; Balaji Venu; John Penton; Emre Ozer 001 (CASES, 2017)

Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. - Emre Ozer 001; Balaji Venu; Xabier Iturbe; Shidhartha Das; Spyros Lyberis; John Biggs; Peter Harrod; John Penton (MICRO, 2018)

Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture. - Xabier Iturbe; Balaji Venu; Juergen Jagst; Emre Ozer 001; Peter Harrod; Chris Turner; John Penton (IEEE Des. Test, 2018)

The Arm Triple Core Lock-Step (TCLS) Processor. - Xabier Iturbe; Balaji Venu; Emre Ozer 001; Jean-Luc Poupat; Gregoire Gimenez; Hans-Ulrich Zurek (ACM Trans. Comput. Syst., 2018)

Tiny Classifier Circuits: Evolving Accelerators for Tabular Data. - Konstantinos Iordanou; Timothy Atkinson 001; Emre Ozer 001; Jedrzej Kufel; John Biggs; Gavin Brown 001; Mikel Luján (CoRR, 2023)

Flexing RISC-V Instruction Subset Processors (RISPs) to Extreme Edge. - Alireza Raisiardali; Konstantinos Iordanou; Jedrzej Kufel; Kowshik Gudimetla; Kris Myny; Emre Ozer 001 (CoRR, 2025)