Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. - Emre Salman; Eby G. Friedman; Ali Dasdan; Feroze Taraporevala; Kayhan Küçükçakar (ISQED, 2006)

Substrate and Ground Noise Interactions in Mixed-Signal Circuits. - Emre Salman; Eby G. Friedman; Radu M. Secareanu (SoCC, 2006)

Substrate Noise Reduction Based On Noise Aware Cell Design. - Emre Salman; Eby G. Friedman; Radu M. Secareanu; Olin L. Hartin (ISCAS, 2007)

Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis. - Emre Salman; Ali Dasdan; Feroze Taraporevala; Kayhan Küçükçakar; Eby G. Friedman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Equivalent rise time for resonance in power/ground noise estimation. - Emre Salman; Eby G. Friedman; Radu M. Secareanu; Olin L. Hartin (ISCAS, 2008)

Input port reduction for efficient substrate extraction in large scale IC's. - Emre Salman; Renatas Jakushokas; Eby G. Friedman; Radu M. Secareanu; Olin L. Hartin (ISCAS, 2008)

Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. - Emre Salman; Eby G. Friedman; Radu M. Secareanu; Olin L. Hartin (ISQED, 2008)

Pseudo-random clocking to enhance signal integrity. - Selçuk Köse; Emre Salman; Zeljko Ignjatovic; Eby G. Friedman (SoCC, 2008)

Contact merging algorithm for efficient substrate noise analysis in large scale circuits. - Emre Salman; Renatas Jakushokas; Eby G. Friedman; Radu M. Secareanu; Olin L. Hartin (ACM Great Lakes Symposium on VLSI, 2009)

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance. - Emre Salman; Eby G. Friedman; Radu M. Secareanu; Olin L. Hartin (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling. - Emre Salman; Eby G. Friedman; Radu M. Secareanu; Olin L. Hartin (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits. - Emre Salman; Renatas Jakushokas; Eby G. Friedman; Radu M. Secareanu; Olin L. Hartin (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Methodology to achieve higher tolerance to delay variations in synchronous circuits. - Emre Salman; Eby G. Friedman (ACM Great Lakes Symposium on VLSI, 2010)

Compact substrate models for efficient noise coupling and signal isolation analysis. - Renatas Jakushokas; Emre Salman; Eby G. Friedman; Radu M. Secareanu; Olin L. Hartin; Cynthia L. Recker (ISCAS, 2010)

Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits. - Emre Salman (ISCAS, 2011)

Shielding Methodologies in the Presence of Power/Ground Noise. - Selçuk Köse; Emre Salman; Eby G. Friedman (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Methodology to determine dominant noise source in a system-on-chip based implantable device. - Zhihua Gan; Emre Salman; Milutin Stanacevic (SoCC, 2012)

Design space exploration for robust power delivery in TSV based 3-D systems-on-chip. - Suhas M. Satheesh; Emre Salman (SoCC, 2012)

Power Distribution in TSV-Based 3-D Processor-Memory Stacks. - Suhas M. Satheesh; Emre Salman (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Utilizing interdependent timing constraints to enhance robustness in synchronous circuits. - Emre Salman; Eby G. Friedman (Microelectron. J., 2012)

Effect of TSV fabrication technology on power distribution in 3D ICs. - Suhas M. Satheesh; Emre Salman (ACM Great Lakes Symposium on VLSI, 2013)

Efficient characterization of TSV-to-transistor noise coupling in 3D ICs. - Hailang Wang; Mohammad H. Asgari; Emre Salman (ACM Great Lakes Symposium on VLSI, 2013)

Power gating topologies in TSV based 3D integrated circuits. - Hailang Wang; Emre Salman (ACM Great Lakes Symposium on VLSI, 2013)

High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design. - Can Sitik; Leo Filippini; Emre Salman; Baris Taskin (ISVLSI, 2014)

Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs. - Hailang Wang; Mohammad H. Asgari; Emre Salman (Integr., 2014)

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks. - Weicheng Liu; Emre Salman; Can Sitik; Baris Taskin (ACM Great Lakes Symposium on VLSI, 2015)

A Novel Static D-Flip-Flop Topology for Low Swing Clocking. - Mallika Rathore; Weicheng Liu; Emre Salman; Can Sitik; Baris Taskin (ACM Great Lakes Symposium on VLSI, 2015)

A wirelessly powered system with charge recovery logic. - Leo Filippini; Emre Salman; Baris Taskin (ICCD, 2015)

Low swing TSV signaling using novel level shifters with single supply voltage. - Shiwei Fang; Emre Salman (ISCAS, 2015)

Enhanced level shifter for multi-voltage operation. - Weicheng Liu; Emre Salman; Can Sitik; Baris Taskin (ISCAS, 2015)

Enhancing system-wide power integrity in 3D ICs with power gating. - Hailang Wang; Emre Salman (ISQED, 2015)

Resource allocation methodology for through silicon vias and sleep transistors in 3D ICs. - Hailang Wang; Emre Salman (ISQED, 2015)

FinFET-Based Low-Swing Clocking. - Can Sitik; Emre Salman; Leo Filippini; Sung-Jun Yoon; Baris Taskin (ACM J. Emerg. Technol. Comput. Syst., 2015)

Quantifying the effect of local interconnects on on-chip power distribution. - Peirong Ji; Emre Salman (Microelectron. J., 2015)

Figures-of-Merit to Evaluate the Significance of Switching Noise in Analog Circuits. - Zhihua Gan; Emre Salman; Milutin Stanacevic (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating. - Hailang Wang; Emre Salman (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs. - Jaya Dofe; Qiaoyan Yu; Hailang Wang; Emre Salman (ACM Great Lakes Symposium on VLSI, 2016)

Transistor-level camouflaged logic locking method for monolithic 3D IC security. - Jaya Dofe; Chen Yan; Scott Kontak; Emre Salman; Qiaoyan Yu (AsianHOST, 2016)

Exploiting useful skew in gated low voltage clock trees. - Weicheng Liu; Emre Salman; Can Sitik; Baris Taskin (ISCAS, 2016)

On-chip hybrid regulator topology for portable SoCs with near-threshold operation. - Yongwan Park; Emre Salman (ISCAS, 2016)

A new circuit design framework for IoT devices: Charge-recycling with wireless power harvesting. - Tutu Wan; Emre Salman; Milutin Stanacevic (ISCAS, 2016)

Design Methodology for Voltage-Scaled Clock Distribution Networks. - Can Sitik; Weicheng Liu; Baris Taskin; Emre Salman (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits. - Jaya Dofe; Zhiming Zhang; Qiaoyan Yu; Chen Yan; Emre Salman (ACM Great Lakes Symposium on VLSI, 2017)

Routing Congestion Aware Cell Library Development for Monolithic 3D ICs. - Chen Yan; Emre Salman (ICRC, 2017)

Energy efficient AC computing methodology for wirelessly powered IoT devices. - Tutu Wan; Yasha Karimi; Milutin Stanacevic; Emre Salman (ISCAS, 2017)

In-package spiral inductor characterization for high efficiency buck converters. - Chen Yan; Zhihua Gan; Emre Salman (ISCAS, 2017)

Open source cell library Mono3D to develop large-scale monolithic 3D integrated circuits. - Chen Yan; Scott Kontak; Hailang Wang; Emre Salman (ISCAS, 2017)

Perspective Paper - Can AC Computing Be an Alternative for Wirelessly Powered IoT Devices? - Tutu Wan; Yasha Karimi; Milutin Stanacevic; Emre Salman (IEEE Embed. Syst. Lett., 2017)

Package-embedded spiral inductor characterization with application to switching buck converters. - Chen Yan; Zhihua Gan; Emre Salman (Microelectron. J., 2017)

Closed-Form Expressions for I/O Simultaneous Switching Noise Revisited. - Hailang Wang; Emre Salman (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Leveraging RF Power for Intelligent Tag Networks. - Emre Salman; Milutin Stanacevic; Samir Ranjan Das; Petar M. Djuric (ACM Great Lakes Symposium on VLSI, 2018)

Error Probability Models to Facilitate Approximate Computing in TFET based Circuits. - Mallika Rathore; Emre Salman (ISCAS, 2018)

Ultra Low Power SIMON Core for Lightweight Encryption. - Tutu Wan; Emre Salman (ISCAS, 2018)

Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs. - Chen Yan; Jaya Dofe; Scott Kontak; Qiaoyan Yu; Emre Salman (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Mono3D: Open Source Cell Library for Monolithic 3-D Integrated Circuits. - Chen Yan; Emre Salman (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs. - Prachi Shukla; Ayse K. Coskun; Vasilis F. Pavlidis; Emre Salman (ACM Great Lakes Symposium on VLSI, 2019)

Low Voltage Clock Tree Synthesis with Local Gate Clusters. - Can Sitik; Weicheng Liu; Baris Taskin; Emre Salman (ACM Great Lakes Symposium on VLSI, 2019)

Signal Shaping at Interface of Wireless Power Harvesting and AC Computational Logic. - Yuanfei Huang; Tutu Wan; Emre Salman; Milutin Stanacevic (ISCAS, 2019)

Power and Data Integrity in Monolithic 3D Integrated SIMON Core. - Ivan Miketic; Emre Salman (ISCAS, 2019)

A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability. - Tasnuva Noor; Emre Salman (ISCAS, 2019)

Frontend Electronic System for Triboelectric Harvester in a Smart Knee Implant. - Manav Jain; Alwathiqbellah Ibrahim; Emre Salman; Milutin Stanacevic; Ryan Willing; Shahrzad Towfighian (MWSCAS, 2019)

SLECTS: Slew-Driven Clock Tree Synthesis. - Weicheng Liu; Can Sitik; Emre Salman; Baris Taskin; Savithri Sundareswaran; Benjamin Huang (IEEE Trans. Very Large Scale Integr. Syst., 2019)

AC Computing Methodology for RF-Powered IoT Devices. - Tutu Wan; Yasha Karimi; Milutin Stanacevic; Emre Salman (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Special Session: Adiabatic Circuits for Energy-Efficient and Secure IoT Systems. - Krithika Dhananjay; Emre Salman (ICCD, 2020)

High Efficiency Fully Integrated On-Chip Regulator for Wide-Range Output Current. - Yongwan Park; Emre Salman (ISCAS, 2020)

Establishing a Covert Communication Channel in RF and mm-Wave Circuits. - Berke Gungor; Melik Yazici; Emre Salman; Yasar Gurbuz (MWSCAS, 2020)

Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration. - Ivan Miketic; Emre Salman (SoCC, 2020)

Error Probability Models for Voltage-Scaled Multiply-Accumulate Units. - Mallika Rathore; Peter A. Milder; Emre Salman (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators. - Prachi Shukla; Sean S. Nemtzow; Vasilis F. Pavlidis; Emre Salman; Ayse K. Coskun (ASP-DAC, 2021)

Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking. - Zhiming Zhang; Ivan Miketic; Emre Salman; Qiaoyan Yu (ACM Great Lakes Symposium on VLSI, 2021)

EQUAL: Efficient QUasi Adiabatic Logic for Enhanced Side-Channel Resistance. - Krithika Dhananjay; Emre Salman (ISVLSI, 2021)

Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques. - Zhiming Zhang; Ivan Miketic; Emre Salman; Qiaoyan Yu (ISVLSI, 2021)

Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects. - Krithika Dhananjay; Prachi Shukla; Vasilis F. Pavlidis; Ayse K. Coskun; Emre Salman (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse Engineering. - Ivan Miketic; Emre Salman (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Session details: Session 2B: Computer-Aided Design (CAD). - Emre Salman (ACM Great Lakes Symposium on VLSI, 2022)

Wireless Power Transfer for Smart Knee Implants. - Manav Jain; Milutin Stanacevic; Ryan Willing; Sherry Towfighian; Emre Salman (ISCAS, 2022)

Temperature-Aware Monolithic 3D DNN Accelerators for Biomedical Applications. - Prachi Shukla; Vasilis F. Pavlidis; Emre Salman; Ayse K. Coskun (CoRR, 2022)

High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors. - Krithika Dhananjay; Vasilis F. Pavlidis; Ayse K. Coskun; Emre Salman (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Power Transfer Optimization for Triboelectric Nanogenerators. - Hosein Haghshenas; Mahmood Chahari; Emre Salman; Ryan Willing; Shahrzad Towfighian; Milutin Stanacevic (BioCAS, 2023)

Precision and Performance-Aware Voltage Scaling in DNN Accelerators. - Mallika Rathore; Peter A. Milder; Emre Salman (ACM Great Lakes Symposium on VLSI, 2023)

Information-Theoretic Perspective to Thermal Covert Channels. - Ivan Miketic; Krithika Yethiraj; Emre Salman (ISCAS, 2023)

Thermal Integrity of ReRAM-based Near-Memory Computing in 3D Integrated DNN Accelerators. - Abrar Abdurrob; Emre Salman; Jack Lombardi (SOCC, 2023)

SEAL-RF: Secure Adiabatic Logic for Wirelessly Powered IoT Devices. - Krithika Dhananjay; Emre Salman (IEEE Internet Things J., 2023)

Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems. - Ivan Miketic; Krithika Dhananjay; Emre Salman (Sensors, 2023)

TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems. - Prachi Shukla; Vasilis F. Pavlidis; Emre Salman; Ayse K. Coskun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Energy-Efficient Dataflow Design for Monolithic 3D Systolic Arrays with Resistive RAM. - Prachi Shukla; Mohammadamin Hajikhodaverdian; Vasilis F. Pavlidis; Emre Salman; Ayse K. Coskun (IGSC, 2024)

Enhanced Detection of Thermal Covert Channel Attacks in Multicore Processors. - Krithika Dhananjay; Vasilis F. Pavlidis; Ayse K. Coskun; Emre Salman (ISQED, 2024)

A Triboelectric Nanogenerator Interface Circuit for Applied Force Sensing. - Hosein Haghshenas; Emre Salman; Ryan Willing; Shahrzad Towfighian; Milutin Stanacevic (MWSCAS, 2024)

A New Dataflow Implementation to Improve Energy Efficiency of Monolithic 3D Systolic Arrays. - Prachi Shukla; Vasilis F. Pavlidis; Emre Salman; Ayse K. Coskun (CoRR, 2024)

PowerID: Using Supply-Side Impedances of Power Delivery Networks as Signatures for Consumer Electronics. - Ivan Miketic; Emre Salman (IEEE Trans. Consumer Electron., 2024)

Leveraging ReRAM Crossbar for Octave Convolution in Deep Neural Networks. - Abrar Abdurrob; Emre Salman (ISCAS, 2025)