An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules. - S. Y. Kim; Emre Tuncer; Rohini Gupta; Byron Krauter; Thomas L. Savarino; Dean P. Neikirk; Lawrence T. Pillage (ICCAD, 1993)

TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects. - Soroush Abbaspour; Amir H. Ajami; Massoud Pedram; Emre Tuncer (ACM Great Lakes Symposium on VLSI, 2004)

Modeling and Propagation of Noisy Waveforms in Static Timing Analysis. - Shahin Nazarian; Massoud Pedram; Emre Tuncer; Tao Lin; Amir H. Ajami (DATE, 2005)

An empirical study of crosstalk in VDSM technologies. - Shahin Nazarian; Massoud Pedram; Emre Tuncer (ACM Great Lakes Symposium on VLSI, 2005)

Sensitivity-Based Gate Delay Propagation in Static Timing Analysis. - Shahin Nazarian; Massoud Pedram; Emre Tuncer; Tao Lin (ISQED, 2005)

CGTA: current gain-based timing analysis for logic cells. - Shahin Nazarian; Massoud Pedram; Tao Lin; Emre Tuncer (ASP-DAC, 2006)

SACI: statistical static timing analysis of coupled interconnects. - Hanif Fatemi; Soroush Abbaspour; Massoud Pedram; Amir H. Ajami; Emre Tuncer (ACM Great Lakes Symposium on VLSI, 2006)

Use of statistical timing analysis on real designs. - A. Nardi; Emre Tuncer; Srinath R. Naidu; A. Antonau; S. Gradinaru; Tao Lin; J. Song (DATE, 2007)

Enabling adaptability through elastic clocks. - Emre Tuncer; Jordi Cortadella; Luciano Lavagno (DAC, 2009)

Chip Placement with Deep Reinforcement Learning. - Azalia Mirhoseini; Anna Goldie; Mustafa Yazgan; Joe W. J. Jiang; Ebrahim M. Songhori; Shen Wang; Young-Joon Lee; Eric Johnson; Omkar Pathak; Sungmin Bae; Azade Nazi; Jiwoo Pak; et al. (CoRR, 2020)

A graph placement methodology for fast chip design. - Azalia Mirhoseini; Anna Goldie; Mustafa Yazgan; Joe Wenjie Jiang; Ebrahim M. Songhori; Shen Wang; Young-Joon Lee; Eric Johnson; Omkar Pathak; Azade Nazi; Jiwoo Pak; Andy Tong; et al. (Nat., 2021)