On accelerating slicing floorplan design with boundary constraints. - En-Cheng Liu; Tu-Hsing Lin; Ting-Chi Wang (ISCAS, 2000)

Power minization in LUT-based FPGA technology mapping. - Zhi-Hong Wang; En-Cheng Liu; Jianbang Lai; Ting-Chi Wang (ASP-DAC, 2001)

Slicing floorplan design with boundary-constrained modules. - En-Cheng Liu; Ming-Shiun Lin; Jianbang Lai; Ting-Chi Wang (ISPD, 2001)

A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction. - Po-Yan Chen; Bing-Ting Ke; Tai-Cheng Lee; I-Ching Tsai; Tai-Wei Kung; Li-Yi Lin; En-Cheng Liu; Yun-Chih Chang; Yih-Lang Li; Mango C.-T. Chao (ISPD, 2022)

Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs. - Li-Wei Chen; Yao-Nien Sui; Tai-Cheng Lee; Yih-Lang Li; Mango C.-T. Chao; I-Ching Tsai; Tai-Wei Kung; En-Cheng Liu; Yun-Chih Chang (ISQED, 2022)