A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. - Wei-Hao Chen; Kai-Xiang Li; Wei-Yu Lin; Kuo-Hsiang Hsu; Pin-Yi Li; Cheng-Han Yang; Cheng-Xin Xue; En-Yu Yang; Yen-Kai Chen; Yun-Sheng Chang; Tzu-Hsiang Hsu; Ya-Chin King; et al. (ISSCC, 2018)

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. - Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xin Si; En-Yu Yang; Xiaoyu Sun 001; Rui Liu 005; Pai-Yu Chen; Qiang Li 021; Shimeng Yu; Meng-Fan Chang (ISSCC, 2018)

AdaptivFloat: A Floating-point based Data Type for Resilient Deep Learning Inference. - Thierry Tambe; En-Yu Yang; Zishen Wan; Yuntian Deng; Vijay Janapa Reddi; Alexander M. Rush; David Brooks 001; Gu-Yeon Wei (CoRR, 2019)

Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference. - Thierry Tambe; En-Yu Yang; Zishen Wan; Yuntian Deng; Vijay Janapa Reddi; Alexander M. Rush; David Brooks 001; Gu-Yeon Wei (DAC, 2020)

EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP. - Thierry Tambe; Coleman Hooper; Lillian Pentecost; En-Yu Yang; Marco Donato; Victor Sanh; Alexander M. Rush; David Brooks 001; Gu-Yeon Wei (CoRR, 2020)

FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference. - En-Yu Yang; Tianyu Jia; David Brooks 001; Gu-Yeon Wei (ASAP, 2021)

SM6: A 16nm System-on-Chip for Accurate and Noise-Robust Attention-Based NLP Applications : The 33rd Hot Chips Symposium - August 22-24, 2021. - Thierry Tambe; En-Yu Yang; Glenn G. Ko; Yuji Chai; Coleman Hooper; Marco Donato; Paul N. Whatmough; Alexander M. Rush; David Brooks 001; Gu-Yeon Wei (HCS, 2021)

9.8 A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET. - Thierry Tambe; En-Yu Yang; Glenn G. Ko; Yuji Chai; Coleman Hooper; Marco Donato; Paul N. Whatmough; Alexander M. Rush; David Brooks 001; Gu-Yeon Wei (ISSCC, 2021)

EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference. - Thierry Tambe; Coleman Hooper; Lillian Pentecost; Tianyu Jia; En-Yu Yang; Marco Donato; Victor Sanh; Paul N. Whatmough; Alexander M. Rush; David Brooks 001; Gu-Yeon Wei (MICRO, 2021)

OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge. - Tianyu Jia; En-Yu Yang; Yu-Shun Hsiao; Jonathan J. Cruz; David Brooks 001; Gu-Yeon Wei; Vijay Janapa Reddi (DATE, 2022)

Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration. - Georgios Zacharopoulos; Adel Ejjeh; Ying Jing; En-Yu Yang; Tianyu Jia; Iulian Brumar; Jeremy Intan; Muhammad Huzaifa; Sarita V. Adve; Vikram S. Adve; Gu-Yeon Wei; David Brooks 001 (CoRR, 2022)

Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration. - Georgios Zacharopoulos; Adel Ejjeh; Ying Jing; En-Yu Yang; Tianyu Jia; Iulian Brumar; Jeremy Intan; Muhammad Huzaifa; Sarita V. Adve; Vikram S. Adve; Gu-Yeon Wei; David Brooks 001 (ACM Trans. Embed. Comput. Syst., 2023)

A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs. - Thierry Tambe; En-Yu Yang; Glenn G. Ko; Yuji Chai; Coleman Hooper; Marco Donato; Paul N. Whatmough; Alexander M. Rush; David Brooks 001; Gu-Yeon Wei (IEEE J. Solid State Circuits, 2023)

14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. - Maico Cassel dos Santos; Tianyu Jia; Joseph Zuckerman; Martin Cochet; Davide Giri; Erik Jens Loscalzo; Karthik Swaminathan; Thierry Tambe; Jeff Jun Zhang; Alper Buyuktosunoglu; Kuan-Lin Chiu; Giuseppe Di Guglielmo; et al. (ISSCC, 2024)