An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques. - Ivan Bietti; Enrico Temporiti; Guido Albasini; Rinaldo Castello (CICC, 2003)

A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications. - Enrico Temporiti; Guido Albasini; Ivan Bietti; Rinaldo Castello; Matteo Colombo (IEEE J. Solid State Circuits, 2004)

A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction. - Colin Weltin-Wu; Enrico Temporiti; Daniele Baldi; Francesco Svelto (ISSCC, 2008)

Insights into wideband fractional All-Digital PLLs for RF applications. - Enrico Temporiti; Colin Weltin-Wu; Daniele Baldi; Riccardo Tonietto; Francesco Svelto (CICC, 2009)

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. - Enrico Temporiti; Colin Weltin-Wu; Daniele Baldi; Riccardo Tonietto; Francesco Svelto (IEEE J. Solid State Circuits, 2009)

A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators. - Federico Vecchi; Stefano Bozzola; Massimo Pozzoni; Davide Guermandi; Enrico Temporiti; Matteo Repossi; Ugo Decanis; Andrea Mazzanti; Francesco Svelto (ISSCC, 2010)

A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. - Colin Weltin-Wu; Enrico Temporiti; Daniele Baldi; Marco Cusmai; Francesco Svelto (ISSCC, 2010)

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation. - Enrico Temporiti; Colin Weltin-Wu; Daniele Baldi; Marco Cusmai; Francesco Svelto (IEEE J. Solid State Circuits, 2010)

Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs. - Colin Weltin-Wu; Enrico Temporiti; Marco Cusmai; Daniele Baldi; Francesco Svelto (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS. - Federico Vecchi; Stefano Bozzola; Enrico Temporiti; Davide Guermandi; Massimo Pozzoni; Matteo Repossi; Marco Cusmai; Ugo Decanis; Andrea Mazzanti; Francesco Svelto (IEEE J. Solid State Circuits, 2011)

A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4. - Dan Li; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Enrico Temporiti; Andrea Mazzanti; Francesco Svelto (ESSCIRC, 2012)

A 5th order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS. - Nicolo Sabatino; Gabriele Minoia; M. Roche; Daniele Baldi; Enrico Temporiti; Andrea Mazzanti (ESSCIRC, 2014)

A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies. - Enrico Temporiti; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Andrea Ghilioni; Francesco Svelto (ESSCIRC, 2014)

FDMA-PON and NG-PON2: Performance and cost comparison. - Silvio Abrate; Roberto Gaudino; Benoît Charbonnier; Sylvie Menezo; Enrico Temporiti; Guang-Hua Duan; Peter O'Brien (ICTON, 2014)

A Low-Noise Design Technique for High-Speed CMOS Optical Receivers. - Dan Li; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Enrico Temporiti; Andrea Mazzanti; Francesco Svelto (IEEE J. Solid State Circuits, 2014)

Power consumption estimation for the silicon-photonics reflective ONU conceived within the FABULOUS European project. - Silvio Abrate; Roberto Gaudino; Benoît Charbonnier; Sylvie Menezo; Enrico Temporiti; Guang-Hua Duan; Peter O'Brien; Guido Giuliani (ICTON, 2015)

22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s. - Marco Cignoli; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Andrea Ghilioni; Enrico Temporiti; Francesco Svelto (ISSCC, 2015)

Silicon photonics and FDMA-PON: Insights from the EU FP7 FABULOUS project. - Silvio Abrate; Roberto Gaudino; Guido Giuliani; Enrico Temporiti; Peter O'Brien; Guang-Hua Duan; Sylvie Menezo; Benoît Charbonnier (OFC, 2015)

Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform. - Frédéric Boeuf; Sebastien Cremer; Enrico Temporiti; Massimo Fere; Mark Shaw 002; Nathalie Vulliet; Bastien Orlando; Delia Ristoiu; Alexis Farcy; Thierry Pinguet; Attila Mekis; Gianlorenzo Masini; et al. (OFC, 2015)

A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links. - Dan Li; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Andrea Ghilioni; Enrico Temporiti; Francesco Svelto (ISCAS, 2016)

23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies. - Enrico Temporiti; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Andrea Ghilioni; Francesco Svelto (ISSCC, 2016)

Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures. - Enrico Temporiti; Andrea Ghilioni; Gabriele Minoia; Piero Orlandi; Matteo Repossi; Daniele Baldi; Francesco Svelto (IEEE J. Solid State Circuits, 2016)

A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With - 15.2-dBm OMA Sensitivity. - Farhad Bozorgi; Melchiorre Bruccoleri; Matteo Repossi; Enrico Temporiti; Andrea Mazzanti; Francesco Svelto (ESSCIRC, 2019)

A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS. - Emanuele Depaoli; Hongyang Zhang; Marco Mazzini; Walter Audoglio; Augusto Andrea Rossi; Guido Albasini; Massimo Pozzoni; Simone Erba; Enrico Temporiti; Andrea Mazzanti (IEEE J. Solid State Circuits, 2019)

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (VLSI Technology and Circuits, 2024)

An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; Domenico Albano; Claudio Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)

A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)