Fully-differential offset-cancelling circuit with configurable output common-mode voltage. - Enrique Alvarez 001; Diego Avila; Hernan Campillo; Angel Abusleme (LASCAS, 2013)

Digital assistance for energy reduction in ADCs using a simple signal prediction algorithm. - Diego Avila; Enrique Alvarez 001; Angel Abusleme (LASCAS, 2014)

Passive reference-sharing SAR ADC. - Enrique Alvarez-Fontecilla; Angel Abusleme (Microelectron. J., 2015)

Canonical Syllogistic Moods in Traditional Aristotelian Logic. - Enrique Alvarez-Fontecilla (Logica Universalis, 2016)

A 64×64 high-density redox amplified coulostatic discharge-based biosensor array in 180nm CMOS. - Alexander Sun; Enrique Alvarez-Fontecilla; A. G. Venkatesh; Eliah Aronoff Spencer; Drew A. Hall (ESSCIRC, 2017)

High-Density Redox Amplified Coulostatic Discharge-Based Biosensor Array. - Alexander Sun; Enrique Alvarez-Fontecilla; A. G. Venkatesh; Eliah Aronoff Spencer; Drew A. Hall (IEEE J. Solid State Circuits, 2018)

Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs. - Enrique Alvarez-Fontecilla; Christian Venerus; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Non-Linearity Compensation Technique for Charge-Redistribution SAR ADCs. - Enrique Alvarez-Fontecilla; Angel Abusleme (LATS, 2019)

Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs. - Enrique Alvarez-Fontecilla; Eslam Helal; Amr I. Eissa; Ian Galton (IEEE J. Solid State Circuits, 2021)

A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL. - Eslam Helal; Enrique Alvarez-Fontecilla; Amr I. Eissa; Ian Galton (IEEE J. Solid State Circuits, 2021)

Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs. - Enrique Alvarez-Fontecilla; Amr I. Eissa; Eslam Helal; Colin Weltin-Wu; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs. - Amr I. Eissa; Enrique Alvarez-Fontecilla; Colin Weltin-Wu; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET. - Junhua Shen; Wei-Hung Chen; Efram Burlingame; Stephen Weinreich; Michael Elliott; Stuart McCracken; Jack Kenney; Janet Brunsilius; Anil Korkmaz; Enrique Alvarez-Fontecilla; Nevena Rakuljic; Ushma Mehta; et al. (ISSCC, 2025)