A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. - Francisco E. Rangel-Patino; Andres Viveros-Wacher; José Ernesto Rayas-Sánchez; Ismael Duron-Rosales; Edgar-Andrei Vega-Ochoa; Nagib Hakim; Enrique Lopez-Miralrio (IEEE Trans. Emerg. Top. Comput., 2020)