Internode: Internal Node Logic Computational Model. - Alejandro Millán 001; Manuel J. Bellido; Jorge Juan-Chico; David Guerrero Martos; Paulino Ruiz-de-Clavijo; Enrique Ostúa (Annual Simulation Symposium, 2003)

Signal Sampling Based Transition Modeling for Digital Gates Characterization. - Alejandro Millán 001; Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; David Guerrero Martos; Enrique Ostúa (PATMOS, 2004)

Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. - Alejandro Millán Calderón; Manuel Jesús Bellido Díaz; Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; David Guerrero Martos; Enrique Ostúa; Julian Viejo (PATMOS, 2005)

Logic-Level Fast Current Simulation for Digital CMOS Circuits. - Paulino Ruiz-de-Clavijo; Jorge Juan-Chico; Manuel Jesús Bellido Díaz; Alejandro Millán Calderón; David Guerrero Martos; Enrique Ostúa; Julian Viejo (PATMOS, 2005)

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. - Julian Viejo; Manuel J. Bellido; Alejandro Millán 001; Enrique Ostúa; Jorge Juan; Paulino Ruiz-de-Clavijo; David Guerrero Martos (IES, 2006)

Accurate Logic-Level Current Estimation for Digital CMOS Circuits. - Paulino Ruiz-de-Clavijo; Jorge Juan-Chico; Manuel Jesús Bellido Díaz; Alejandro Millán 001; David Guerrero Martos; Enrique Ostúa; Julian Viejo (J. Low Power Electron., 2006)

Static Power Consumption in CMOS Gates Using Independent Bodies. - David Guerrero Martos; Alejandro Millán 001; Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Enrique Ostúa; Julian Viejo (PATMOS, 2007)

Design of a FFT/IFFT module as an IP core suitable for embedded systems. - Julian Viejo; Alejandro Millán 001; Manuel J. Bellido; Jorge Juan; Paulino Ruiz-de-Clavijo; David Guerrero Martos; Enrique Ostúa; Alejandro Muñoz (SIES, 2007)

Improving the Performance of Static CMOS Gates by Using Independent Bodies. - David Guerrero Martos; Alejandro Millán 001; Jorge Juan-Chico; Manuel Jesús Bellido Díaz; Paulino Ruiz-de-Clavijo; Enrique Ostúa; Julian Viejo (J. Low Power Electron., 2007)

Design and implementation of a suitable core for on-chip long-term verification. - Julian Viejo; Jose Ignacio Villar; Jorge Juan; Alejandro Millán 001; Manuel Jesús Bellido Díaz; Enrique Ostúa (SIES, 2010)

Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. - David Guerrero Martos; Alejandro Millán 001; Jorge Juan; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Enrique Ostúa; Julian Viejo (J. Low Power Electron., 2011)

Long-term on-chip verification of systems with logical events scattered in time. - Julian Viejo; Jose Ignacio Villar; Jorge Juan; Alejandro Millán 001; Enrique Ostúa; Juan Quiros (Microprocess. Microsystems, 2012)

Minimalistic SDHC-SPI hardware reader module for boot loader applications. - Paulino Ruiz-de-Clavijo; Enrique Ostúa; Manuel Jesús Bellido Díaz; Jorge Juan; Julian Viejo; David Guerrero Martos (Microelectron. J., 2017)

Using the complement of the cosine to compute trigonometric functions. - David Guerrero Martos; Alejandro Millán Calderón; Jorge Juan-Chico; Julian Viejo; Manuel Jesús Bellido Díaz; Paulino Ruiz-de-Clavijo; Enrique Ostúa (EURASIP J. Adv. Signal Process., 2020)

Address-encoded byte order. - David Guerrero Martos; German Cano-Quiveu; Jorge Juan-Chico; Alejandro Millán 001; Manuel J. Bellido; Julian Viejo; Paulino Ruiz-de-Clavijo; Enrique Ostúa (Microprocess. Microsystems, 2020)