A scalable loop optimization approach for scalable DSP processors. - Jian Wang 046; Bogong Su; Erh-Wen Hu (ICASSP, 2000)

De-pipeline a software-pipelined loop. - Bogong Su; Jian Wang 046; Erh-Wen Hu; Joseph B. Manzano (ICASSP (2), 2003)

Loop optimization with tradeoff between cycle count and code size for DSP applications. - Bogong Su; Jian Wang 046; Rafi Rabipour; Erh-Wen Hu; Joseph B. Manzano (EUSIPCO, 2004)

Software De-Pipelining Technique. - Bogong Su; Jian Wang 046; Erh-Wen Hu; Joseph B. Manzano (SCAM, 2004)

New DSP Benchmark based on Selectable Mode Vocoder (SMV). - Erh-Wen Hu; Cyril Ku; Andrew Russo; Bogong Su; Jian Wang 046 (CDES, 2006)

Software performance prediction at source level. - Erh-Wen Hu; Bogong Su; Jian Wang 046 (SERA, 2017)

Comparing DSP Software Performance Prediction Models at Source Code Level - From Analytical to Statistical. - Erh-Wen Hu; Weihua Liu; Bogong Su; Jian Wang 046 (J. Softw., 2019)

Using machine learning techniques for DSP software performance prediction at source code level. - Weihua Liu; Erh-Wen Hu; Bogong Su; Jian Wang 046 (Connect. Sci., 2021)