Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC with 85.1 dB DR and 91 dB SFDR. - Lukang Shi; Eashwar Thaigarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (MWSCAS, 2020)

Low-Distortion Correlated Level Shifting Sample-and-Hold Stage. - Alexander Pierce; Eashwar Thaigarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (NEWCAS, 2021)

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR. - Lukang Shi; Eashwar Thiagarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Multi-Residue Two-Step Incremental ADC. - Faraz Adin; Hanyu Wang; Lukang Shi; Rajiv Singh; Erhan Hancioglu; Gabor C. Temes (MWSCAS, 2024)

98-dB SNDR Multi-Residue Two-Step Incremental ADC With Two-Capacitor SAR. - Faraz Adin; Hanyu Wang; Lukang Shi; Rajiv Singh; Erhan Hancioglu; Gabor C. Temes (IEEE Trans. Circuits Syst. II Express Briefs, 2025)