A 60x60 Processor Array Smart Sensor for Binary Image Processung. - A. Reichart; Patrick Garda; Eric Belhaire; Francis J. Devos; Bertrand Y. Zavidovique (MVA, 1988)

Two analog counters for neural network implementation. - Kurosh Madani; Patrick Garda; Eric Belhaire; Francis Devos (IEEE J. Solid State Circuits, 1991)

An optoelectronic CMOS circuit implementing a simulated annealing algorithm. - Antoine Dupret; Eric Belhaire; Jean-Claude Rodier; Philippe Lalanne; Donald Prevost; Patrick Garda; Pierre Chavel (IEEE J. Solid State Circuits, 1996)

Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications. - Amir Kazéminéjad; Eric Belhaire (DFT, 2001)

TAS-MRAM based Non-volatile FPGA logic circuit. - Weisheng Zhao; Eric Belhaire; Bernard Dieny; Guillaume Prenat; Claude Chappert (FPT, 2007)

CMOS/Magnetic Hybrid Architectures. - Guillaume Prenat; Mourad El Baraji; Wei Guo; Ricardo Sousa; Liliana Buda-Prejbeanu; Bernard Dieny; Virgile Javerliac; Jean-Pierre Nozieres; Weisheng Zhao; Eric Belhaire (ICECS, 2007)

Synthesis of Finite State Machines with Magnetic Domain Wall Logic. - Jacques-Olivier Klein; Eric Belhaire; Claude Chappert; Florent Ouchet; Russell Cowburn; Dan Read; Dorothee Petit (ISCAS, 2007)

Spintronic Device Based Non-volatile Low Standby Power SRAM. - Weisheng Zhao; Eric Belhaire; Claude Chappert; Pascale Mazoyer (ISVLSI, 2008)

Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit. - Weisheng Zhao; Eric Belhaire; Claude Chappert; Pascale Mazoyer (ACM Trans. Embed. Comput. Syst., 2009)

TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. - Weisheng Zhao; Eric Belhaire; Claude Chappert; Bernard Dieny; Guillaume Prenat (ACM Trans. Reconfigurable Technol. Syst., 2009)