Signal propagation in high-speed MCM circuits. - Claudio Truzzi; Eric Beyne; Edwin Ringoot; J. Peeters (ICCD, 1995)

Design of Test Modules for the Analysis of MCM Interconnects. - Claudio Truzzi; Eric Beyne; Edwin Ringoot (ED&TC, 1996)

Chip-package codesign of a low-power 5-GHz RF front end. - Stéphane Donnay; Philip Pieters; Kristof Vaesen; Wim Diels; Piet Wambacq; Walter De Raedt; Eric Beyne; Marc Engels; Ivo Bolsens (Proc. IEEE, 2000)

The influence of packaging materials on RF performance. - Arun Chandrasekhar; Steven Brebels; Serguei Stoukatch; Eric Beyne; Walter De Raedt; Bart Nauwelaers (Microelectron. Reliab., 2003)

Direct gold and copper wires bonding on copper. - Hong Meng Ho; Wai Lam; Serguei Stoukatch; Petar Ratchev; Charles J. Vath; Eric Beyne (Microelectron. Reliab., 2003)

Advantage of In-situ over Ex-situ techniques as reliability tool: Aging kinetics of Imec's MCM-D discrete passives devices. - Philippe Soussan; G. Lekens; R. Dreesen; Ward De Ceuninck; Eric Beyne (Microelectron. Reliab., 2003)

Modified micro-macro thermo-mechanical modelling of ceramic ball grid array packages. - Bart Vandevelde; Dominiek Degryse; Eric Beyne; Eric Roose; Dorina Corlatan; Guido Swaelen; Geert Willems; Filip Christiaens; Alcatel Bell; Dirk Vandepitte (Microelectron. Reliab., 2003)

Characterization and FE analysis on the shear test of electronic materials. - Marcel Gonzalez; Bart Vandevelde; R. Van Hoof; Eric Beyne (Microelectron. Reliab., 2004)

Package level interconnect options. - J. Balachandran; Steven Brebels; Geert Carchon; Tomas Webers; Walter De Raedt; Bart Nauwelaers; Eric Beyne (SLIP, 2005)

Analysis and modeling of power grid transmission lines. - J. Balachandran; Steven Brebels; Geert Carchon; Tomas Webers; Walter De Raedt; Bart Nauwelaers; Eric Beyne (DATE, 2006)

Active Electrode Arrays by Chip Embedding in a Flexible Silicone Carrier. - Mathieu Vanden Bulcke; Kris Baert; Eric Beyne; Mario Gonzalez; Christophe Winters; Tomas Webers (EMBC, 2006)

Constant Impedance Scaling Paradigm for Scaling LC transmission lines. - J. Balachandran; Steven Brebels; Geert Carchon; Walter De Raedt; Eric Beyne; Maarten Kuijk; Bart Nauwelaers (ISQED, 2006)

Efficient Link Architecture for On-Chip Serial links and Networks. - J. Balachandran; Maarten Kuijk; Steven Brebels; Geert Carchon; Walter De Raedt; Bart Nauwelaers; Eric Beyne (SoC, 2006)

Constant impedance scaling paradigm for interconnect synthesis. - J. Balachandran; Steven Brebels; Geert Carchon; Maarten Kuijk; Walter De Raedt; Bart Nauwelaers; Eric Beyne (SLIP, 2006)

Technologies for highly miniaturized autonomous sensor networks. - Kris Baert; Bert Gyselinckx; Tom Torfs; Vladimir Leonov; Refet Firat Yazicioglu; Steven Brebels; Stéphane Donnay; J. Vanfletern; M. Pastreen; Eric Beyne; Chris Van Hoof (Microelectron. J., 2006)

Wafer-level package interconnect options. - J. Balachandran; Steven Brebels; Geert Carchon; Maarten Kuijk; Walter De Raedt; Bart Nauwelaers; Eric Beyne (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Tutorial T7A: Advanced IC Packaging. - Eric Beyne (VLSI Design, 2007)

Thermal cycling reliability of SnAgCu and SnPb solder joints: A comparison for several IC-packages. - Bart Vandevelde; Mario Gonzalez; Paresh Limaye; Petar Ratchev; Eric Beyne (Microelectron. Reliab., 2007)

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. - Yann Civale; Deniz Sabuncuoglu Tezcan; Harold G. G. Philipsen; P. Jaenen; Rahul Agarwal; F. Duval; Philippe Soussan; Youssef Travaly; Eric Beyne (3DIC, 2009)

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). - Jan Van Olmen; Jan Coenen; Wim Dehaene; Kristin De Meyer; Cedric Huyghebaert; Anne Jourdain; Guruprasad Katti; Abdelkarim Mercha; Michal Rakowski; Michele Stucchi; Youssef Travaly; Eric Beyne; et al. (3DIC, 2009)

Impact of 3D design choices on manufacturing cost. - Dimitrios Velenis; Michele Stucchi; Erik Jan Marinissen; Bart Swinnen; Eric Beyne (3DIC, 2009)

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot. - Paul Marchal; Bruno Bougard; Guruprasad Katti; Michele Stucchi; Wim Dehaene; Antonis Papanikolaou; Diederik Verkest; Bart Swinnen; Eric Beyne (Proc. IEEE, 2009)

A novel concept for ultra-low capacitance via-last TSV. - Yann Civale; Marcel Gonzalez; Deniz Sabuncuoglu Tezcan; Youssef Travaly; Philippe Soussan; Eric Beyne (3DIC, 2010)

300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications. - Anne Jourdain; Thibault Buisson; Alain Phommahaxay; Mark Privett; Dan Wallace; Sumant Sood; Peter Bisson; Eric Beyne; Youssef Travaly; Bart Swinnen (3DIC, 2010)

Cost effectiveness of 3D integration options. - Dimitrios Velenis; Erik Jan Marinissen; Eric Beyne (3DIC, 2010)

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. - Geert Van der Plas; Steven Thijs; Dimitri Linten; Guruprasad Katti; Paresh Limaye; Abdelkarim Mercha; Michele Stucchi; Herman Oprins; Bart Vandevelde; Nikolaos Minas; Miro Cupac; Morin Dehan; et al. (CICC, 2010)

Design issues and considerations for low-cost 3D TSV IC technology. - Geert Van der Plas; Paresh Limaye; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Domae Shinichi; Vladimir Cherman; et al. (ISSCC, 2010)

In-tier diagnosis of power domains in 3D TSV ICs. - Yuuki Araga; Makoto Nagata; Geert Van der Plas; Jaemin Kim; Nikolaos Minas; Pol Marchal; Youssef Travaly; Michael Libois; Antonio La Manna; Wenqi Zhang; Eric Beyne (3DIC, 2011)

Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices - Technology directions. - Eric Beyne (3DIC, 2011)

In-line metrology and inspection for process control during 3D stacking of IC's. - Sandip Halder; Ingrid De Wolf; Alain Phommahaxay; Andy Miller; Mireille Maenhoudt; Gerald Beyer; Bart Swinnen; Eric Beyne (3DIC, 2011)

3D stacking using Cu-Cu direct bonding. - Y. H. Hu; C. S. Liu; M. J. Lii; Kenneth J. Rebibis; Anne Jourdain; Antonio La Manna; Gerald Beyer; Eric Beyne; C. H. Yu (3DIC, 2011)

Analysis of microbump induced stress effects in 3D stacked IC technologies. - Andrej Ivankovic; Geert Van der Plas; V. Moroz; M. Choi; Vladimir Cherman; Abdelkarim Mercha; Paul Marchal; Marcel Gonzalez; Geert Eneman; Wenqi Zhang; Thibault Buisson; Mikael Detalle; et al. (3DIC, 2011)

3D stacking using ultra thin dies. - Antonio La Manna; Dimitrios Velenis; Thibault Buisson; Mikael Detalle; Kenneth J. Rebibis; Wenqi Zhang; Eric Beyne (3DIC, 2011)

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding. - Alain Phommahaxay; Anne Jourdain; Greet Verbinnen; Tobias Woitke; Peter Bisson; Markus Gabriel; Walter Spiess; Alice Guerrero; Jeremy McCutcheon; Rama Puligadda; Pieter Bex; Axel Van den Eede; et al. (3DIC, 2011)

3D heterogeneous system integration: application driver for 3D technology development. - Eric Beyne; Pol Marchal; Geert Van der Plas (DAC, 2011)

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. - Geert Eneman; J. Cho; V. Moroz; Dragomir Milojevic; M. Choi; Kristin De Meyer; Abdelkarim Mercha; Eric Beyne; Thomas Hoffmann 001; Geert Van der Plas (DATE, 2011)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Geert Van der Plas; Paresh Limaye; Igor Loi; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Vladimir Cherman; et al. (IEEE J. Solid State Circuits, 2011)

Cu pumping in TSVs: Effect of pre-CMP thermal budget. - Ingrid De Wolf; Kris Croes; O. Varela Pedreira; Riet Labie; Augusto Redolfi; M. Van De Peer; Kris Vanstreels; C. Okoro; Bart Vandevelde; Eric Beyne (Microelectron. Reliab., 2011)

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. - Wei Guo; Geert Van der Plas; Andrej Ivankovic; Geert Eneman; Vladimir Cherman; Bart De Wachter; Abdelkarim Mercha; Mario Gonzalez; Yann Civale; Augusto Redolfi; Thibault Buisson; A. Jourdan; et al. (ICICDT, 2012)

Si interposer build-up options and impact on 3D system cost. - Dimitrios Velenis; Mikael Detalle; Erik Jan Marinissen; Eric Beyne (3DIC, 2013)

Design issues in heterogeneous 3D/2.5D integration. - Dragomir Milojevic; Pol Marchal; Erik Jan Marinissen; Geert Van der Plas; Diederik Verkest; Eric Beyne (ASP-DAC, 2013)

Analysis of 3D interconnect performance: Effect of the Si substrate resistivity. - X. Sun; Geert Van der Plas; Mikael Detalle; Eric Beyne (3DIC, 2014)

Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges. - Joeri De Vos; Vladimir Cherman; Mikael Detalle; Teng Wang; Abdellah Salahouelhadj; Robert Daily; Geert Van der Plas; Eric Beyne (3DIC, 2014)

System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform. - Prashant Agrawal; Dragomir Milojevic; Praveen Raghavan; Francky Catthoor; Liesbet Van der Perre; Eric Beyne; Ravi Varadarajan (IEEE Embed. Syst. Lett., 2014)

Fast convolution based thermal model for 3D-ICs: Methodology, accuracy analysis and package impact. - F. L. T. Maggioni; Herman Oprins; Eric Beyne; Ingrid De Wolf; Martine Baelmans (Microelectron. J., 2014)

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias. - Yunlong Li; Stefaan Van Huylenbroeck; Els Van Besien; Xiaoping Shi; Chen Wu; Michele Stucchi; Gerald Beyer; Eric Beyne; Ingrid De Wolf; Kristof Croes (Microelectron. Reliab., 2014)

Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling. - Bart Vandevelde; Andrej Ivankovic; B. Debecker; Melina Lofrano; Kris Vanstreels; Wei Guo; Vladimir Cherman; Marcel Gonzalez; Geert Van der Plas; Ingrid De Wolf; Eric Beyne; Zsolt Tokei (Microelectron. Reliab., 2014)

3D system integration research at IMEC. - Eric Beyne (3DIC, 2015)

Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics. - Soon-Wook Kim; Lan Peng; Andy Miller; Gerald Beyer; Eric Beyne; Chung-Sun Lee (3DIC, 2015)

Processing active devices on Si interposer and impact on cost. - Dimitrios Velenis; Mikael Detalle; Geert Hellings; Mirko Scholz; Erik Jan Marinissen; Geert Van der Plas; Antonio La Manna; Andy Miller; Dimitri Linten; Eric Beyne (3DIC, 2015)

Through silicon via to FinFET noise coupling in 3-D integrated circuits. - A. Rouhi Najaf Abadi; W. Guo; X. Sun; K. Ben Ali; Jean-Pierre Raskin; Martin Rack; C. Roda Neve; M. Choi; V. Moroz; Geert Van der Plas; Ingrid De Wolf; Eric Beyne; et al. (ICICDT, 2015)

Thermal experimental and modeling analysis of high power 3D packages. - Herman Oprins; Vladimir Cherman; Geert Van der Plas; F. L. T. Maggioni; Joeri De Vos; Eric Beyne (ICICDT, 2015)

Impact of oxide liner properties on TSV Cu pumping and TSV stress. - Joke De Messemaeker; O. Varela Pedreira; A. Moussa; Nabi Nabiollahi; Kris Vanstreels; Stefaan Van Huylenbroeck; Harold Philipsen; Patrick Verdonck; Bart Vandevelde; Ingrid De Wolf; Eric Beyne; Kris Croes (IRPS, 2015)

Active-lite interposer for 2.5 & 3D integration. - Geert Hellings; Mirko Scholz; Mikael Detalle; Dimitrios Velenis; Muriel de Potter de ten Broeck; C. Roda Neve; Y. Li; Stefaan Van Huylenbroeck; Shih-Hung Chen; Erik Jan Marinissen; Antonio La Manna; Geert Van der Plas; et al. (VLSIC, 2015)

Microstructure simulation of grain growth in Cu through silicon vias using phase-field modeling. - Nabi Nabiollahi; Nele Moelans; Mario Gonzalez; Joke De Messemaeker; Christopher J. Wilson; Kristof Croes; Eric Beyne; Ingrid De Wolf (Microelectron. Reliab., 2015)

Die to wafer 3D stacking for below 10um pitch microbumps. - Jaber Derakhshandeh; Lin Hou; Inge De Preter; Carine Gerets; Samuel Suhard; Vikas Dubey; Geraldine Jamieson; Fumihiro Inoue; Tomas Webers; Pieter Bex; Giovanni Capuz; Eric Beyne; et al. (3DIC, 2016)

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. - Stefaan Van Huylenbroeck; Yunlong Li; Michele Stucchi; Lieve Bogaerts; Joeri De Vos; Gerald Beyer; Eric Beyne; Mohand Brouri; Praveen Nalla; Sanjay Gopinath; Matthew Thorum; Joe Richardson; et al. (3DIC, 2016)

Extreme wafer thinning optimization for via-last applications. - Anne Jourdain; Joeri De Vos; Fumihiro Inoue; Kenneth J. Rebibis; Andy Miller; Gerald Beyer; Eric Beyne; Edward Walsby; Jash Patel; Oliver Ansell; Janet Hopkins; Huma Ashraf; et al. (3DIC, 2016)

High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer. - C. Roda Neve; Mikael Detalle; Philip Nolmans; Yunlong Li; Joeri De Vos; Geert Van der Plas; Gerald Beyer; Eric Beyne (3DIC, 2016)

Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects. - Joeri De Vos; Lan Peng; Alain Phommahaxay; Joost Van Ongeval; Andy Miller; Eric Beyne; Florian Kurz; Thomas Wagenleiter; Markus Wimplinger; Thomas Uhrmann (3DIC, 2016)

The 3-D Interconnect Technology Landscape. - Eric Beyne (IEEE Des. Test, 2016)

Reliability Challenges Related to TSV Integration and 3-D Stacking. - Kristof Croes; Joke De Messemaeker; Yunlong Li; Wei Guo; Olalla Varela Pedreira; Vladimir Cherman; Michele Stucchi; Ingrid De Wolf; Eric Beyne (IEEE Des. Test, 2016)

Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices. - Kristof J. P. Jacobs; T. Wang; Michele Stucchi; Mario Gonzalez; Kris Croes; Ingrid De Wolf; Eric Beyne (Microelectron. Reliab., 2017)

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects. - Luka Kljucar; Mario Gonzalez; Kristof Croes; Ingrid De Wolf; Joke De Messemaeker; Gayle Murdoch; Philip Nolmans; Joeri De Vos; Jürgen Bömmels; Eric Beyne; Zsolt Tökei (Microelectron. Reliab., 2017)

Stress mitigation of 3D-stacking/packaging induced stresses. - Kristof Croes; Vladimir Cherman; Melina Lofrano; Houman Zahedmanesh; Luka Kljucar; Mario Gonzalez; Ingrid De Wolf; Zsolt Tökei; Eric Beyne (IRPS, 2018)

TSV process-induced MOS reliability degradation. - Yunlong Li; Michele Stucchi; Stefaan Van Huylenbroeck; Geert Van der Plas; Gerald Beyer; Eric Beyne; Kristof Croes (IRPS, 2018)

A study on substrate noise coupling among TSVs in 3D chip stack. - Yuuki Araga; Makoto Nagata; Joeri De Vos; Geert Van der Plas; Eric Beyne (IEICE Electron. Express, 2018)

Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly. - Melina Lofrano; Vladimir Cherman; Mario Gonzalez; Eric Beyne (Microelectron. Reliab., 2018)

Protective Layer for Collective Die to Wafer Hybrid Bonding. - Fumihiro Inoue; Julien Bertheau; Samuel Suhard; Alain Phommahaxay; Takuya Ohashi; Tetsuro Kinoshita; Yohei Kinoshita; Eric Beyne (3DIC, 2019)

Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. - Giuliano Sisto; Peter Debacker; Rongmei Chen; Geert Van der Plas; Richard Chou; Eric Beyne; Dragomir Milojevic (3DIC, 2019)

Process Complexity and Cost Considerations of Multi-Layer Die Stacks. - Dimitrios Velenis; Joeri De Vos; Soon-Wook Kim; Jaber Derakhshandeh; Pieter Bex; Giovanni Capuz; Samuel Suhard; Kenneth June Rebibis; Stefaan Van Huylenbroeck; Erik Jan Marinissen; Alain Phommahaxay; Andy Miller; et al. (3DIC, 2019)

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited). - Giuliano Sisto; Rongmei Chen; Richard Chou; Geert Van der Plas; Eric Beyne; Rod Metcalfe; Dragomir Milojevic (SLIP, 2021)

Design and Technology Solutions for 3D Integrated High Performance Systems. - Geert Van der Plas; Eric Beyne (VLSI Circuits, 2021)

Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy. - Kristof J. P. Jacobs; Michele Stucchi; Eric Beyne (IEEE Trans. Instrum. Meas., 2021)

Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism. - Lin Hou; Emmanuel Chery; Kristof Croes; Davide Tierno; Soon Aik Chew; Yangyin Chen; Peter Rakbin; Eric Beyne (IRPS, 2022)

Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. - Rongmei Chen; Giuliano Sisto; Odysseas Zografos; Dragomir Milojevic; Pieter Weckx; Geert Van der Plas; Eric Beyne (SLIP, 2022)

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. - Rongmei Chen; Giuliano Sisto; Michele Stucchi; Anne Jourdain; Kenichi Miyaguchi; Pieter Schuddinck; P. Woeltgens; H. Lin; Naveen Kakarla; Anabela Veloso; Dragomir Milojevic; Odysseas Zografos; et al. (VLSI Technology and Circuits, 2022)

(Why do we need) Wireless Heterogeneous Integration (anyway?). - Michaël Peeters; S. Sinha; Xiao Sun; Claude Desset; Giuseppe Gramegna; John Slabbekoorn; Pieter Bex; Nelson Pinho; Tomas Webers; Dimitrios Velenis; Andy Miller; Nadine Collaert; et al. (VLSI Technology and Circuits, 2022)

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. - Kateryna Serbulova; S.-H. Chen; Geert Hellings; Anabela Veloso; Anne Jourdain; Dimitri Linten; Jo De Boeck; Guido Groeseneken; Julien Ryckaert; Geert Van der Plas; Eric Beyne; Eugenio Dentoni Litta; et al. (VLSI Technology and Circuits, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Efficient Backside Power Delivery for High-Performance Computing Systems. - Hesheng Lin; Geert Van der Plas; Xiao Sun; Dimitrios Velenis; Francky Catthoor; Rudy Lauwereins; Eric Beyne (IEEE Trans. Very Large Scale Integr. Syst., 2022)

84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. - Hesheng Lin; Dimitrios Velenis; Philip Nolmans; Xiao Sun; Francky Catthoor; Rudy Lauwereins; Geert Van der Plas; Eric Beyne (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs. - Mohamed Naeim; Hanqi Yang; Pinhong Chen; Rong Bao; Antoine Dekeyser; Giuliano Sisto; Moritz Brunion; Rongmei Chen; Geert Van der Plas; Eric Beyne; Dragomir Milojevic (3DIC, 2023)

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. - Xabier Iturbe; Nassim Abderrahmane; Jaume Abella 001; Sergi Alcaide; Eric Beyne; Henri-Pierre Charles; Christelle Charpin-Nicolle; Lars Chittka; Angélica Dávila; Arne Erdmann; Carles Estrada; Ander Fernández; et al. (DATE, 2023)

Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN). - Eric Beyne; Anne Jourdain; Gerald Beyer (VLSI Technology and Circuits, 2023)

IP Session on Chiplet: Design, Assembly, and Test. - Bapi Vinnakota; Jaber Derakhshandeh; Eric Beyne; Erik Jan Marinissen; Sreejit Chakravarty (VTS, 2023)

Impact of gate-level clustering on automated system partitioning of 3D-ICs. - Quentin Delhaye; Eric Beyne; Joël Goossens; Geert Van der Plas; Dragomir Milojevic (Microelectron. J., 2023)

Clean Dicing: An Alternative Blade Dicing Technique for Minimising Particles in 3D Heterogeneous Integration. - Akito Hiro; Damien Jon Leech; Geert Schoofs; John Slabbekoorn; Alain Phommahaxay; Koen Kennes; Gerald Beyer; Eric Beyne (3DIC, 2024)

Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology. - S.-H. Lin; Marko Simicic; N. Pantano; S.-H. Chen; Geert Van der Plas; Eric Beyne; Piet Wambacq (VLSI Technology and Circuits, 2024)

Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. - P. Zhao; Liesbeth Witters; Anne Jourdain; Michele Stucchi; Nicolas Jourdan 002; J. W. Maes; H. Bana; C. Zhu; R. Chukka; F. Sebaai; Kevin Vandersmissen; N. Heylen; et al. (VLSI Technology and Circuits, 2024)

Reliability Study of La- and Al-Doped ZrO2 Dielectrics for High Density MIMCAP Applications. - Emmanuel Chery; Lucie Sourgen; Jacopo Franco; Mihaela Ioana Popovici; Eric Beyne (IRPS, 2025)