Strategic directions towards multicore application specific computing. - Eric Flamand (DATE, 2009)

PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status. - Christian Fabre; Iuliana Bacivarov; Ananda Basu; Martino Ruggiero; David Atienza; Eric Flamand; Jean-Pierre Krimm; Julien Mottin; Lars Schor; Pratyush Kumar; Hoeseok Yang; Devesh B. Chokshi; et al. (FMCO, 2011)

Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications. - Diego Melpignano; Luca Benini; Eric Flamand; Bruno Jego; Thierry Lepley; Germain Haugou; Fabien Clermidy; Denis Dutoit (DAC, 2012)

P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator. - Luca Benini; Eric Flamand; Didier Fuin; Diego Melpignano (DATE, 2012)

PRO3D: programming for future 3D manycore architectures. - Christian Fabre; Iuliana Bacivarov; Eth Zürich; Ananda Basu; Martino Ruggiero; David Atienza; Eric Flamand (INA-OCMC@HiPEAC, 2012)

A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory. - Thierry Lepley; Pierre G. Paulin; Eric Flamand (CASES, 2013)

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Cristiano Santos; Fabien Clermidy; Séverine Cheramy; Frédéric Pétrot; et al. (ISSCC, 2016)

Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. - Pasquale Davide Schiavone; Francesco Conti 001; Davide Rossi; Michael Gautschi; Antonio Pullini; Eric Flamand; Luca Benini (PATMOS, 2017)

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. - Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; Frank K. Gürkaynak; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2017)

GAP-8: A RISC-V SoC for AI at the Edge of the IoT. - Eric Flamand; Davide Rossi; Francesco Conti 001; Igor Loi; Antonio Pullini; Florent Rotenberg; Luca Benini (ASAP, 2018)

Always-ON visual node with a hardware-software event-based binarized neural network inference engine. - Manuele Rusci; Davide Rossi; Eric Flamand; Massimo Gottardi; Elisabetta Farella; Luca Benini (CF, 2018)

The transprecision computing paradigm: Concept, design, and applications. - A. Cristiano I. Malossi; Michael Schaffner; Anca Molnos; Luca Gammaitoni; Giuseppe Tagliavini; Andrew P. J. Emerson; Andrés Tomás; Dimitrios S. Nikolopoulos; Eric Flamand; Norbert Wehn (DATE, 2018)

Ultra Low Power Deep-Learning-powered Autonomous Nano Drones. - Daniele Palossi; Antonio Loquercio; Francesco Conti 001; Eric Flamand; Davide Scaramuzza 001; Luca Benini (CoRR, 2018)

A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones. - Daniele Palossi; Antonio Loquercio; Francesco Conti 001; Eric Flamand; Davide Scaramuzza 001; Luca Benini (IEEE Internet Things J., 2019)

Integer-Only Approximated MFCC for Ultra-Low Power Audio NN Processing on Multi-Core MCUs. - Marco Fariselli; Manuele Rusci; Joel Cambonie; Eric Flamand (AICAS, 2021)

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Stefan Mach; Alfio Di Mauro; Marco Guermandi; Giuseppe Tagliavini; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (ISSCC, 2021)

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (CoRR, 2021)

Accelerating RNN-Based Speech Enhancement on a Multi-core MCU with Mixed FP16-INT8 Post-training Quantization. - Manuele Rusci; Marco Fariselli; Martin Croome; Francesco Paci; Eric Flamand (PKDD/ECML Workshops (1), 2022)

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (IEEE J. Solid State Circuits, 2022)

Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters. - Jie Chen 042; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi (CoRR, 2023)

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. - Jie Chen 042; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Self-Learning for Personalized Keyword Spotting on Ultra-Low-Power Audio Sensors. - Manuele Rusci; Francesco Paci; Marco Fariselli; Eric Flamand; Tinne Tuytelaars (CoRR, 2024)

Self-Learning for Personalized Keyword Spotting on Ultralow-Power Audio Sensors. - Manuele Rusci; Francesco Paci; Marco Fariselli; Eric Flamand; Tinne Tuytelaars (IEEE Internet Things J., 2025)