A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. - John Davis; Don Plass; Paul Bunce; Yuen H. Chan; Antonio Pelella; Rajiv V. Joshi; A. Chen; William V. Huott; Thomas J. Knips; Pradip Patel; K. Lo; Eric Fluhr (ISSCC, 2006)

Design of the Power6 Microprocessor. - Joshua Friedrich; Bradley D. McCredie; Norman K. James; Bill Huott; Brian W. Curran; Eric Fluhr; Gaurav Mittal; Eddie Chan; Yuen H. Chan; Donald W. Plass; Sam G. Chu; Hung Q. Le; et al. (ISSCC, 2007)

Power-constrained high-frequency circuits for the IBM POWER6 microprocessor. - Brian W. Curran; Eric Fluhr; Jose Paredes; Leon J. Sigal; Joshua Friedrich; Yiu-Hing Chan; Charlie Hwang (IBM J. Res. Dev., 2007)

Design and Implementation of the POWER6 Microprocessor. - Benjamin Stolt; Yonatan Mittlefehldt; Sanjay Dubey; Gaurav Mittal; Mike Lee; Joshua Friedrich; Eric Fluhr (IEEE J. Solid State Circuits, 2008)

Session 3 overview: Processors. - Se-Hyun Yang; Eric Fluhr (ISSCC, 2013)

POWER8 design methodology innovations for improving productivity and reducing power. - Matthew M. Ziegler; Ruchir Puri; Bob Philhower; Robert L. Franch; Wing K. Luk; Jens Leenstra; Peter Verwegen; Niels Fricke; George Gristede; Eric Fluhr; Victor V. Zyuban (CICC, 2014)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

F3: Adaptive design techniques for energy efficiency. - Eric Fluhr; Michael Polley; Se-Hyun Yang; Vasantha Erraguntla; Tobias Noll; Kees van Berkel 001 (ISSCC, 2014)

F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. - Ken Chang; Frank O'Mahony; Elad Alon; Hyeon-Min Bae; Nicola Da Dalt; Eric Fluhr (ISSCC, 2015)

Physical design and implementation of POWER8™ (P8) server class processor. - Mozammel Hossain; Eric Fluhr; Allen Hall; Vikas Agarwal (MWSCAS, 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

Session 8 overview: Low-power digital circuits. - Eric Fluhr; Bing Sheu (ISSCC, 2016)

Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. - Debjit Sinha; Vladimir Zolotov; Eric Fluhr; Michael H. Wood; Jeffrey Ritzinger; Natesan Venkateswaran; Stephen Shuma (VLSID, 2016)

A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology. - Philipp Salz; A. Frisch; Wolfgang Penth; J. Noack; T. Kalla; Rolf Sautter; Michael Kugel; Otto A. Torreiter; G. Sapp; Mike Lee; Eric Fluhr; A. Rozenfeld; et al. (ESSCIRC, 2017)

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. - Michael S. Floyd; Phillip J. Restle; Michael A. Sperling; Pawel Owczarczyk; Eric J. Fluhr; Joshua Friedrich; Paul Muench; Timothy Diemoz; Pierce Chuang; Christos Vezyrtzis (ISSCC, 2017)

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. - Christopher J. Gonzalez; Eric Fluhr; Daniel Dreps; David Hogenmiller; Rahul M. Rao; Jose Paredes; Michael S. Floyd; Michael A. Sperling; Ryan Kruse; Vinod Ramadurai; Ryan Nett; Md. Saiful Islam 004; et al. (ISSCC, 2017)

IBM POWER9 circuit design and energy optimization for 14-nm technology. - Eric J. Fluhr; Rahul M. Rao; Howard Smith; Alper Buyuktosunoglu; Ramon Bertran Monfort (IBM J. Res. Dev., 2018)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. - Rahul M. Rao; Christopher J. Gonzalez; Eric Fluhr; Abraham Mathews; Andrew Bianchi; Daniel Dreps; David Wolpert 001; Eric Lai; Gerald Strevig; Glen A. Wiedemeier; Philipp Salz; Ryan Kruse (ISSCC, 2022)

Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor. - Brian T. Vanderpool; Phillip J. Restle; Eric J. Fluhr; Gregory S. Still; Frank Campisano; Ian Carmichael; Eric Marz; Rahul Batra; Richard L. Willaman (ISSCC, 2022)

Deterministic Frequency and Voltage Enhancements on the POWER10 Processor. - Brian T. Vanderpool; Phillip J. Restle; Eric Fluhr; Gregory S. Still; Francesco A. Campisano; Ian Charmichael; Eric Marz; Rahul Batra; Richard L. Willaman (IEEE J. Solid State Circuits, 2023)