Adaptive Stackable 3D Cache Architecture for Manycores. - Eric Guthmuller; Ivan Miro Panades; Alain Greiner (ISVLSI, 2012)

3D integration for power-efficient computing. - Denis Dutoit; Eric Guthmuller; Ivan Miro Panades (DATE, 2013)

3D stacking for multi-core architectures: From WIDEIO to distributed caches. - Fabien Clermidy; Denis Dutoit; Eric Guthmuller; Ivan Miro Panades; Pascal Vivet (ISCAS, 2013)

Architectural exploration of a fine-grained 3D cache for high performance in a manycore context. - Eric Guthmuller; Ivan Miro Panades; Alain Greiner (VLSI-SoC, 2013)

3D advanced integration technology for heterogeneous systems. - Pascal Vivet; Christian Bernard; Fabien Clermidy; Denis Dutoit; Eric Guthmuller; Ivan Miro Panades; Gaël Pillonnet; Yvain Thonnart; Arnaud Garnier; Didier Lattard; Amandine Jouve; Franck Bana; et al. (3DIC, 2015)

Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. - Pascal Vivet; Christian Bernard; Eric Guthmuller; Ivan Miro Panades; Yvain Thonnart; Fabien Clermidy (ISVLSI, 2015)

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols. - Julie Dumas; Eric Guthmuller; César Fuguet Tortolero; Frédéric Pétrot (ARCS, 2017)

Trace-driven exploration of sharing set management strategies for cache coherence in manycores. - Julie Dumas; Eric Guthmuller; César Fuguet Tortolero; Frédéric Pétrot (NEWCAS, 2017)

Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach. - Julie Dumas; Eric Guthmuller; Frédéric Pétrot (ASAP, 2018)

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. - Eric Guthmuller; César Fuguet Tortolero; Pascal Vivet; Christian Bernard; Ivan Miro Panades; Jean Durupt; E. Beignc; Didier Lattard; Séverine Cheramy; Alain Greiner; Quentin L. Meunier; Pirouz Bazargan-Sabet (ESSCIRC, 2018)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

Storage Class Memory with Computing Row Buffer: A Design Space Exploration. - Valentin Egloff; Jean-Philippe Noel; Maha Kooli; Bastien Giraud; Lorenzo Ciampolini; Roman Gauchi; César Fuguet Tortolero; Eric Guthmuller; Mathieu Moreau; Jean-Michel Portal (DATE, 2021)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)

Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor. - Yves Durand; Eric Guthmuller; César Fuguet Tortolero; Jérôme Fereyre; Andrea Bocco; Riccardo Alidori (ARITH, 2022)

A Scalable Low-Latency FPGA Architecture for Spin Qubit Control Through Direct Digital Synthesis. - Mathieu Toubeix; Eric Guthmuller; Adrian Evans; Tristan Meunier (DATE, 2024)

A Variable and Extended Precision (VRP) Accelerator and its 22 nm SoC Implementation. - César Fuguet; Eric Guthmuller; Andrea Bocco; Jérôme Fereyre; Adrian Evans; Yves Durand (DCIS, 2024)

Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation. - Eric Guthmuller; César Fuguet; Andrea Bocco; Jérôme Fereyre; Riccardo Alidori; Ihsane Tahir; Yves Durand (IEEE Trans. Computers, 2024)