A routing algorithm for flip-chip design. - Jia-Wei Fang; I-Jye Lin; Ping-Hung Yuh; Yao-Wen Chang; Jyh-Herng Wang (ICCAD, 2005)

An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. - Jia-Wei Fang; Chin-Hsiung Hsu; Yao-Wen Chang (DAC, 2007)

ECO timing optimization using spare cells. - Yen-Pin Chen; Jia-Wei Fang; Yao-Wen Chang (ICCAD, 2007)

A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design. - Jia-Wei Fang; I-Jye Lin; Yao-Wen Chang; Jyh-Herng Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Area-I/O flip-chip routing for chip-package co-design. - Jia-Wei Fang; Yao-Wen Chang (ICCAD, 2008)

Routing for chip-package-board co-design considering differential pairs. - Jia-Wei Fang; Kuan-Hsien Ho; Yao-Wen Chang (ICCAD, 2008)

Flip-chip routing with unified area-I/O pad assignments for package-board co-design. - Jia-Wei Fang; Martin D. F. Wong; Yao-Wen Chang (DAC, 2009)

An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. - Jia-Wei Fang; Chin-Hsiung Hsu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews. - Jia-Wei Fang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

ECO Timing Optimization Using Spare Cells and Technology Remapping. - Kuan-Hsien Ho; Yen-Pin Chen; Jia-Wei Fang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

IR to routing challenge and solution for interposer-based design. - Eric Jia-Wei Fang; Terry Chi-Jih Shih; Darton Shen-Yu Huang (ASP-DAC, 2015)

Machine-learning-based dynamic IR drop prediction for ECO. - Yen-Chun Fang; Heng-Yi Lin; Min-Yan Su; Chien-Mo James Li; Eric Jia-Wei Fang (ICCAD, 2018)

IR drop prediction of ECO-revised circuits using machine learning. - Shih-Yao Lin 001; Yen-Chun Fang; Yu-Ching Li; Yu-Cheng Liu; Tsung-Shan Yang; Shang-Chien Lin; Chien-Mo James Li; Eric Jia-Wei Fang (VTS, 2018)

Automatic IR-Drop ECO Using Machine Learning. - Heng-Yi Lin; Yen-Chun Fang; Shi-Tang Liu; Jia-Xian Chen; Chien-Mo James Li; Eric Jia-Wei Fang (ITC-Asia, 2020)

35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC. - Bo-Jr Huang; Eric Jia-Wei Fang; Sung S.-Y. Hsueh; Rory Huang; Angus Lin; Chi-Hsun Chiang; Yi-Hsuan Lin; Wen-Wen Hsieh; Barry Chen; Yi-Chang Zhuang; Cheng-Yuh Wu; Jia-Ming Chen; et al. (ISSCC, 2021)

Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning. - Yen-Ting Kuo; Wei-Chen Lin; Chun Chen; Chao-Ho Hsieh; James Chien-Mo Li; Eric Jia-Wei Fang; Sung S.-Y. Hsueh (ITC, 2021)

Chip Performance Prediction Using Machine Learning Techniques. - Min-Yan Su; Wei-Chen Lin; Yen-Ting Kuo; Chien-Mo James Li; Eric Jia-Wei Fang; Sung S.-Y. Hsueh (VLSI-DAT, 2021)

ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption. - Wei-Chen Lin; Chun Chen; Chao-Ho Hsieh; James Chien-Mo Li; Eric Jia-Wei Fang; Sung S.-Y. Hsueh (ITC, 2022)

Optimal Camera Placement for 6 Degree-of-Freedom Immersive Video Streaming Without Accessing 3D Scenes. - Sheng-Ming Tang; Yuan-Chun Sun; Jia-Wei Fang; Kuan-Yu Lee; Ching-Ting Wang; Cheng-Hsin Hsu (IXR@MM, 2022)

Enhancing situational awareness with adaptive firefighting drones: leveraging diverse media types and classifiers. - Tzu-Yi Fan; Fangqi Liu 001; Jia-Wei Fang; Nalini Venkatasubramanian; Cheng-Hsin Hsu (MMSys, 2022)

A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET. - Bo-Jr Huang; Alfred Tsai; Lear Hsieh; Kathleen Chang; C.-J. Tsai; Jia-Ming Chen; Eric Jia-Wei Fang; Sung S.-Y. Hsueh; Jack Ciao; Barry Chen; Chuck Chang; Ping Kao; et al. (ISSCC, 2023)

Modeling Gamer Quality-of-Experience Using a Real Cloud VR Gaming Testbed. - Kuan-Yu Lee; Jia-Wei Fang; Yuan-Chun Sun; Cheng-Hsin Hsu (MMVE@MMSys, 2023)

Will Dynamic Foveation Boost Cloud VR Gaming Experience? - Jia-Wei Fang; Kuan-Yu Lee; Teemu Kämäräinen; Matti Siekkinen; Cheng-Hsin Hsu (NOSSDAV, 2023)

Vmin Prediction Using Nondestructive Stress Test. - Chun Chen; Jeng-Yu Liao; James Chien-Mo Li; Harry H. Chen; Eric Jia-Wei Fang (VTS, 2023)

14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU. - Chien-Yu Lu; Bo-Jr Huang; Min-Chieh Chen; Ollie Tsai; Alfred Tsai; Eric Jia-Wei Fang; Yuju Cho; Harry H. Chen; Ping Kao; Ericbill Wang; Hugh Mair; Shih-Arn Hwang (ISSCC, 2024)

8.2: Run-Time Power Management System by on-Die Power Sensor with Silicon Machine Learning-Based Calibration in a 3nm Octa-Core CPU. - Chien-Yu Lu; Bo-Jr Huang; Min-Chieh Chen; Alfred Tsai; Eric Jia-Wei Fang; Yuju Cho; Rex Che-Yuan Liu; Ericbill Wang; You-Ming Tsao; Hugh Mair; Shih-Arn Hwang (ISSCC, 2025)