Timing error correction techniques for voltage-scalable on-chip memories. - Eric Karl; Dennis Sylvester; David T. Blaauw (ISCAS (4), 2005)

Reliability modeling and management in dynamic microprocessor-based systems. - Eric Karl; David T. Blaauw; Dennis Sylvester; Trevor N. Mudge (DAC, 2006)

ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon. - Dennis Sylvester; David T. Blaauw; Eric Karl (IEEE Des. Test Comput., 2006)

Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. - Eric Karl; Dennis Sylvester; David T. Blaauw (ISQED, 2008)

Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation. - Eric Karl; Prashant Singh; David T. Blaauw; Dennis Sylvester (ISSCC, 2008)

Multi-Mechanism Reliability Modeling and Management in Dynamic Systems. - Eric Karl; David T. Blaauw; Dennis Sylvester; Trevor N. Mudge (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Sensor-Driven Reliability and Wearout Management. - Prashant Singh; Cheng Zhuo; Eric Karl; David T. Blaauw; Dennis Sylvester (IEEE Des. Test Comput., 2009)

Dynamic NBTI management using a 45nm multi-degradation sensor. - Prashant Singh; Eric Karl; Dennis Sylvester; David T. Blaauw (CICC, 2010)

A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. - Hyunwoo Nho; Pramod Kolar; Fatih Hamzaoglu; Yih Wang; Eric Karl; Yong-Gee Ng; Uddalak Bhattacharya; Kevin Zhang 001 (ISSCC, 2010)

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. - Pramod Kolar; Eric Karl; Uddalak Bhattacharya; Fatih Hamzaoglu; Henry Nho; Yong-Gee Ng; Yih Wang; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2011)

Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor. - Prashant Singh; Eric Karl; Dennis Sylvester; David T. Blaauw (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (ISSCC, 2012)

Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation. - Prashant Singh; Eric Karl; David T. Blaauw; Dennis Sylvester (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Mesut Meterelliyoz; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (IEEE J. Solid State Circuits, 2013)

17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. - Eric Karl; Zheng Guo; James W. Conary; Jeffrey L. Miller; Yong-Gee Ng; Satyanand Nalam; Daeyeon Kim; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001 (ISSCC, 2015)

A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products. - Chia-Hong Jan; F. Al-amoody; H.-Y. Chang; T. Chang; Y.-W. Chen; N. Dias; Walid M. Hafez; Doug B. Ingerly; M. Jang; Eric Karl; S. K.-Y. Shi; K. Komeyli; et al. (VLSIC, 2015)

A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. - Kyung-Hoae Koo; Liqiong Wei; John Keane 001; Uddalak Bhattacharya; Eric A. Karl; Kevin Zhang 001 (VLSIC, 2015)

17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. - John Keane 001; Jaydeep Kulkarni; Kyung-Hoae Koo; Satyanand Nalam; Zheng Guo; Eric Karl; Kevin Zhang 001 (ISSCC, 2016)

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. - Eric Karl; Zheng Guo; James W. Conary; Jeffrey L. Miller; Yong-Gee Ng; Satyanand Nalam; Daeyeon Kim; John Keane 001; Xiaofei Wang; Uddalak Bhattacharya; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2016)

5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. - Jaydeep P. Kulkarni; John Keane 001; Kyung-Hoae Koo; Satyanand Nalam; Zheng Guo; Eric Karl; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2017)

A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications. - Zheng Guo; Daeyeon Kim; Satyanand Nalam; Jami Wiedemer; Xiaofei Wang; Eric Karl (ISSCC, 2018)

A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications. - Zheng Guo; Daeyeon Kim; Satyanand Nalam; Jami Wiedemer; Xiaofei Wang; Eric Karl (IEEE J. Solid State Circuits, 2019)

A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead. - Zheng Guo; Jami Wiedemer; Yusung Kim 002; Prithvee Sundararajan Ramamoorthy; Prateeksha Bindiganavile Sathyaprasad; Smita Shridharan; Daeyeon Kim; Eric Karl (VLSI Circuits, 2020)

F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets. - Christopher Gonzalez; Huichu Liu; Mijung Noh; Eric Karl; Thomas Toifl; Shawn S. H. Hsu (ISSCC, 2021)

Session 24 Overview: Advanced Embedded Memories Memory Subcommittee. - Eric Karl; Shinichiro Shiratake; Jonathan Chang (ISSCC, 2021)

SE1: What Technologies Will Shape the Future of Computing? - Hugh Mair; Shinichiro Shiratake; Eric Karl; Thomas Burd; Jonathan Chang; Debbie Marr; Samuel Naffziger; Henk Corporaal; Ken Takeuchi; Naresh R. Shanbhag (ISSCC, 2021)

Investigating Barriers for the Adoption of the German Contact-Tracing App and the Influence of a Video Intervention on User Acceptance. - Victoria Böhm; Christian Wolff 001; Corinna Geiselhart; Eric Karl; Nina Kleindienst (MuC, 2021)

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). - Friedel Gerfers; Ping-Hsuan Hsieh; Dejan Markovic; Jun Deguchi; Eric Karl (IEEE J. Solid State Circuits, 2021)

Advances in Microprocessor Cache Architectures Over the Last 25 Years. - Ravi R. Iyer 001; Vivek De; Ramesh Illikkal; David A. Koufaty; Bhushan Chitlur; Andrew Herdrich; Muhammad M. Khellah; Fatih Hamzaoglu; Eric Karl (IEEE Micro, 2021)

Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing. - Wilfred Gomes; Altug Koker; Patrick N. Stover; Doug B. Ingerly; Scott Siers; Srikrishnan Venkataraman; Chris Pelto; Tejas Shah; Amreesh Rao; Frank O'Mahony; Eric Karl; Lance Cheney; et al. (ISSCC, 2022)

A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology. - Stafford Hutchins; Jiabo Li; Atresh Sanne; Zhanping Chen; Mohammad M. Hasan; Uddalak Bhattacharya; Eric Karl; Jaydeep P. Kulkarni (VLSI Technology and Circuits, 2022)

E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology. - M. Shamanna; E. Abuayob; G. Aenuganti; C. Alvares; J. Antony; A. Bahudhanam; A. Chandran; P. Chew; A. Chatterjee; B. Chauhan; N. Dandeti; J. Desai; et al. (VLSI Technology and Circuits, 2023)

Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology. - Yusung Kim 002; Clifford Ong; Anandkumar Mahadevan Pillai; Harish Jagadeesh; Gwanghyeon Baek; Iqbal Rajwani; Zheng Guo; Eric Karl (IEEE J. Solid State Circuits, 2023)

15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia. - Daeyeon Kim; Yusung Kim 002; Ayush Shrivastava; Gyusung Park; Anandkumar Mahadevan Pillai; Kunal Bannore; Tri Doan; Muktadir Rahman; Gwanghyeon Baek; Clifford Ong; Xiaofei Wang; Zheng Guo; et al. (ISSCC, 2024)

An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications. - Walid M. Hafez; D. Abanulo; M. Abdelkader; S. An; C. Auth; D. Bahr; V. Balakrishnan; Rohan Bambery; M. Beck; M. Bhargava; S. Bhowmick; J. Biggs-houck; et al. (VLSI Technology and Circuits, 2024)

29.2 A 0.021µm2 High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery. - Xiaofei Wang; Yusung Kim 002; Gwanghyeon Baek; Kunal Girish Bannore; Kaushal Dave; Arash Joushaghani; Narae Kang; Minwoo Ko; Anandkumar Mahadevan Pillai; Hema Chandra Prakash Movva; Gyusung Park; Muktadir Rahman; et al. (ISSCC, 2025)