Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits. - Eric Liau; Doris Schmitt-Landsiedel (ETW, 2003)

Evolution of automatic semiconductor test equipment: automatic test pattern learning, classification, optimisation and generation for power supply noise. - Eric Liau; Doris Schmitt-Landsiedel (VECIMS, 2003)

Computational Intelligence Characterization Method of Semiconductor Device. - Eric Liau; Doris Schmitt-Landsiedel (DATE, 2005)

Computational intelligence based testing for semiconductor measurement systems. - Eric Liau; Doris Schmitt-Landsiedel (ITC, 2005)

A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation. - Thomas Janik; Eric Liau; Harald Lorenz; Manfred Menke; Eckehard Plaettner; Joerg Schweden; Helmut Seitz; Esther Vega-Ordonez (ISCAS, 2006)

Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing. - Eric Liau Chee Hong; Manfred Menke; Thomas Janik; Doris Schmitt-Landsiedel (ITC, 2006)

Fully automated semiconductor operating condition testing. - Thomas Nirmaier; Wolfgang Spirkl; Eric Liau Chee Hong (ITC, 2006)

Efficient High-Speed Interface Verification and Fault Analysis. - Thomas Nirmaier; Jose Torres Zaguirre; Eric Liau; Wolfgang Spirkl; Armin Rettenberger; Doris Schmitt-Landsiedel (ITC, 2008)