GAUT: An architectural synthesis tool for dedicated signal processors. - Eric Martin 001; Olivier Sentieys; Hélène Dubois; Jean Luc Philippe (EURO-DAC, 1993)

Hardware interface design for real time embedded systems. - Adel Baganne; Jean Luc Philippe; Eric Martin 001 (Great Lakes Symposium on VLSI, 1997)

Adaptive filters implementation performances under power dissipation constraint. - Stephane Gailhard; Nathalie Julien; Eric Martin 001 (EUSIPCO, 1998)

How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. - S. Gailhard; Nathalie Julien; Jean-Philippe Diguet; Eric Martin 001 (Great Lakes Symposium on VLSI, 1998)

Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. - S. Gailhard; Nathalie Julien; Adel Baganne; Eric Martin 001 (Great Lakes Symposium on VLSI, 1999)

Architectural Synthesis with Interconnection Cost Control. - Christophe Jégo; Emmanuel Casseau; Eric Martin 001 (VLSI, 1999)

A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller. - Adel Baganne; Jean Luc Philippe; Eric Martin 001 (J. VLSI Signal Process., 1999)

Architectural synthesis of digital signal processing applications dedicated to submicron technologies. - Emmanuel Casseau; Christophe Jégo; Eric Martin 001 (ICECS, 2001)

A smart "single line" pixel sensor for industrial vision. - Eric Senn; D. Emzivat; Eric Martin 001 (ICECS, 2001)

A Vision System on Chip for Industrial Control. - Eric Senn; Eric Martin 001 (VLSI-SOC, 2001)

A design methodology for integrating IP into SOC systems. - Philippe Coussy; Adel Baganne; Eric Martin 001 (CICC, 2002)

IP cores integration in DSP System-on-chip designs. - Philippe Coussy; Adel Baganne; Eric Martin 001 (EUSIPCO, 2002)

High-level design verification using Taylor Expansion Diagrams: first results. - Priyank Kalla; Maciej J. Ciesielski; Emmanuel Boutillon; Eric Martin 001 (HLDVT, 2002)

Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder. - Philippe Coussy; Adel Baganne; Eric Martin 001 (ICECS, 2002)

A design methodology for IP integration. - Philippe Coussy; Adel Baganne; Eric Martin 001 (ISCAS (4), 2002)

Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor. - Nathalie Julien; Johann Laurent; Eric Senn; Eric Martin 001 (ISHPC, 2002)

Power Consumption Estimation of a C Program for Data-Intensive Applications. - Eric Senn; Nathalie Julien; Johann Laurent; Eric Martin 001 (PATMOS, 2002)

A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration. - Adel Baganne; Imed Bennour; Mehrez Elmarzougui; Riadh Gaiech; Eric Martin 001 (DATE, 2003)

A simulation based approach for incorporating virtual components IP cores into multimedia systems design. - Adel Baganne; Imed Bennour; Mehrez Elmarzougui; Eric Martin 001 (ICASSP (2), 2003)

Communication and Timing Constraints Analysis for IP Design and Integration. - Philippe Coussy; Adel Baganne; Eric Martin 001 (VLSI-SOC, 2003)

Power Consumption Modeling and Characterization of the TI C6201. - Nathalie Julien; Johann Laurent; Eric Senn; Eric Martin 001 (IEEE Micro, 2003)

Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT. - Nathalie Julien; S. Gailhard; Eric Martin 001 (J. VLSI Signal Process., 2003)

Memory accesses management during high level synthesis. - Gwenolé Corre; Eric Senn; Pierre Bomel; Nathalie Julien; Eric Martin 001 (CODES+ISSS, 2004)

Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. - Johann Laurent; Nathalie Julien; Eric Senn; Eric Martin 001 (DATE, 2004)

Memory Aware HLS and the Implementation of Ageing Vectors. - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (DSD, 2004)

Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. - David Elléouet; Nathalie Julien; Dominique Houzet; Jean-Gabriel Cousin; Eric Martin 001 (DSD, 2004)

A Complete Methodology for Memory Optimization in DSP Applications. - Florian Marteil; Nathalie Julien; Eric Senn; Eric Martin 001 (DSD, 2004)

A memory aware behavioral synthesis tool for real-time VLSI circuits. - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (ACM Great Lakes Symposium on VLSI, 2004)

A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder. - Philippe Coussy; David Gnaedig; Amor Nafkha; Adel Baganne; Emmanuel Boutillon; Eric Martin 001 (ICASSP (5), 2004)

Reed-Solomon behavioral virtual component for communication systems. - Emmanuel Casseau; Bertrand Le Gal; Christophe Jégo; Nathalie Le Heno; Eric Martin 001 (ISCAS (4), 2004)

A Memory Aware High Level Synthesis Tool . - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (ISVLSI, 2004)

SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. - Eric Senn; Johann Laurent; Nathalie Julien; Eric Martin 001 (PATMOS, 2004)

Synthèse d'architecture pour la réalisation comportementale de l'algorithme MAP pour Turbo Décodeur. - David Gnaedig; Emmanuel Boutillon; Eric Martin 001; Amor Nafkha; Michel Jézéquel; Jacky Tousch; Nathalie Brengarth (Ann. des Télécommunications, 2004)

Synthèse architecturale d'applications temps réel pour technologies submicroniques. - Emmanuel Casseau; Christophe Jégo; Eric Martin 001 (Tech. Sci. Informatiques, 2004)

Synchronization Processor Synthesis for Latency Insensitive Systems. - Pierre Bomel; Eric Martin 001; Emmanuel Boutillon (DATE, 2005)

High-Level Synthesis in Latency Insensitive System Methodology. - Pierre Bomel; Nabil Abdelli; Eric Martin 001; Anne-Marie Fouilliart; Emmanuel Boutillon; Philippe Kajfasz (DSD, 2005)

C-based rapid prototyping for digital signal processing. - Emmanuel Casseau; Bertrand Le Gal; Pierre Bomel; Christophe Jégo; Sylvain Huet; Eric Martin 001 (EUSIPCO, 2005)

Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. - Bertrand Le Gal; Emmanuel Casseau; Eric Martin 001 (EUSIPCO, 2005)

SystemCmantic: A high level Modelling and Co-Design Framework. - Lobna Kriaa; S. Adriano; Emmanuel Vaumorin; R. Nouacer; F. Blanc; S. Pajaniardja; Philippe Coussy; Eric Martin 001; Dominique Heller; Farhat Thabet; Anne-Marie Fouilliart (FDL, 2005)

A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. - Philippe Coussy; Gwenolé Corre; Pierre Bomel; Eric Senn; Eric Martin 001 (ICASSP (5), 2005)

High-level synthesis under I/O timing and memory constraints. - Philippe Coussy; Gwenolé Corre; Eric Senn; Pierre Bomel; Eric Martin 001 (ISCAS (1), 2005)

Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. - Bertrand Le Gal; Emmanuel Casseau; Sylvain Huet; Eric Martin 001 (ISVLSI, 2005)

DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. - Pierre Bomel; Nabil Abdelli; Eric Martin 001; Anne-Marie Fouilliart; Emmanuel Boutillon; Philippe Kajfasz (SAMOS, 2005)

SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications. - Eric Senn; Johann Laurent; Nathalie Julien; Eric Martin 001 (EURASIP J. Adv. Signal Process., 2005)

Design Space Exploration of DSP Applications Based on Behavioral Description Models. - Farhat Thabet; Philippe Coussy; Dominique Heller; Eric Martin 001 (SiPS, 2006)

Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power - Gwenolé Corre; Nathalie Julien; Eric Senn; Eric Martin 001 (CoRR, 2006)

A Memory Aware High Level Synthesis Too - Gwenolé Corre; Nathalie Julien; Eric Senn; Eric Martin 001 (CoRR, 2006)

Memory Aware High-Level Synthesis for Embedded Systems - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (CoRR, 2006)

Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI - Gwenolé Corre; Philippe Coussy; Pierre Bomel; Eric Senn; Eric Martin 001 (CoRR, 2006)

Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. - Guillaume Savaton; Emmanuel Casseau; Eric Martin 001 (Signal Process., 2006)

A formal method for hardware IP design and integration under I/O and timing constraints. - Philippe Coussy; Emmanuel Casseau; Pierre Bomel; Adel Baganne; Eric Martin 001 (ACM Trans. Embed. Comput. Syst., 2006)

G729 Voice Decoder Design. - Fatma Sayadi; Emmanuel Casseau; Mohamed Atri; Mehrez Marzougui; Rached Tourki; Eric Martin 001 (J. VLSI Signal Process., 2006)

Application of a design space exploration tool to enhance interleaver generation. - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (EUSIPCO, 2007)

Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system. - Farhat Thabet; Philippe Coussy; Dominique Heller; Eric Martin 001 (EUSIPCO, 2007)

A design methodology for space-time adapter. - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (ACM Great Lakes Symposium on VLSI, 2007)

A design flow dedicated to multi-mode architectures for DSP applications. - Cyrille Chavet; Caaliph Andriamisaina; Philippe Coussy; Emmanuel Casseau; Emmanuel Juin; Pascal Urard; Eric Martin 001 (ICCAD, 2007)

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (ISCAS, 2007)

Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (CoRR, 2007)

Constrained algorithmic IP design for system-on-chip. - Philippe Coussy; Emmanuel Casseau; Pierre Bomel; Adel Baganne; Eric Martin 001 (Integr., 2007)

Estimation et optimisation de la consommation des mémoires. - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (Tech. Sci. Informatiques, 2008)

Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. - Farhat Thabet; Philippe Coussy; Dominique Heller; Eric Martin 001 (J. Signal Process. Syst., 2009)

Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. - Ghizlane Lhairech-Lebreton; Philippe Coussy; Eric Martin 001 (FPL, 2010)

Static Address Generation Easing: a design methodology for parallel interleaver architectures. - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (ICASSP, 2010)

Bitwidth-aware high-level synthesis for designing low-power DSP applications. - Ghizlane Lhairech-Lebreton; Philippe Coussy; Dominique Heller; Eric Martin 001 (ICECS, 2010)

Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. - Awais Sani; Philippe Coussy; Cyrille Chavet; Eric Martin 001 (ICECS, 2010)

A methodology based on Transportation problem modeling for designing parallel interleaver architectures. - Awais Sani; Philippe Coussy; Cyrille Chavet; Eric Martin 001 (ICASSP, 2011)

An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. - Awais Sani; Philippe Coussy; Cyrille Chavet; Eric Martin 001 (ISCAS, 2011)

A design approach dedicated to network-based and conflict-free parallel interleavers. - Aroua Briki; Cyrille Chavet; Philippe Coussy; Eric Martin 001 (ACM Great Lakes Symposium on VLSI, 2012)

Typology of Manufacturing Digital Twins: A First Step Towards a Deployment Methodology. - Nathalie Julien; Eric Martin 001 (SOHOMA, 2021)

How Humans Comply With a (Potentially) Faulty Robot: Effects of Multidimensional Transparency. - Loïck Simon; Clément Guérin; Philippe Rauffet; Christine Chauvin; Eric Martin 001 (IEEE Trans. Hum. Mach. Syst., 2023)