Combined DRAM and logic chip for massively parallel systems. - Peter M. Kogge; Toshio Sunaga; Hisatada Miyataka; Koji Kitamura; Eric Retter (ARVLSI, 1995)

A parallel processing chip with embedded DRAM macros. - Toshio Sunaga; Hisatada Miyatake; Koji Kitamura; Peter M. Kogge; Eric Retter (IEEE J. Solid State Circuits, 1996)

IBM POWER9 memory architectures for optimized systems. - William J. Starke; J. S. Dodson; Jeffrey Stuecheli; Eric Retter; Brad W. Michael; Stephen J. Powell; James A. Marcella (IBM J. Res. Dev., 2018)